Patents by Inventor Cheng Xu
Cheng Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071873Abstract: The present invention discloses a package structure for reducing warpage of plastic package wafer, including an adapter board, a chip mounted on the adapter board, and a first plastic package layer covering the chip, through-silicon-vias are disposed on the adapter board, the first and second surfaces of the adapter board are respectively provided with external connection solder balls and/or external connection solder pads electrically connected with the through-silicon-vias. The process of manufacturing the package structure includes: after the first surface process of the adapter board is completed, bonding the first carrier on its first surface, then cutting the first carrier to expose the chip-mounting area, and then carrying out subsequent processes such as chip mounting, and finally cutting and removing the first carrier to complete the package.Type: ApplicationFiled: March 5, 2021Publication date: February 29, 2024Applicants: NATIONAL CENTER FOR ADVANCED PACKAGING CO., LTD, SHANGHAI XIANFANG SEMICONDUCTOR CO., LTDInventors: Liqiang CAO, Cheng XU, Peng SUN, Fei GENG
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Patent number: 11901115Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.Type: GrantFiled: July 26, 2022Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Kyu-Oh Lee, Rahul Jain, Sai Vadlamani, Cheng Xu, Ji Yong Park, Junnan Zhao, Seo Young Kim
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Patent number: 11894282Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.Type: GrantFiled: June 19, 2019Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Zhimin Wan, Sergio Antonio Chan Arguedas, Peng Li, Chandra Mohan Jha, Aravindha R. Antoniswamy, Cheng Xu, Junnan Zhao, Ying Wang
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Patent number: 11891924Abstract: A rocker arm mechanism includes a rocker arm shaft, a rocker arm, a valve clearance adjuster, a valve train, and a control valve. The rocker arm is rotatably disposed on the rocker arm shaft. The valve train includes a valve bridge. The rocker arm is provided with a plunger chamber. The valve clearance adjuster includes a hydraulic tappet slidably disposed in the plunger chamber. The plunger chamber is supplied with oil through an oil supply passage. The control valve is configured to open or close the oil supply passage. When the control valve opens the oil supply passage, the hydraulic tappet can abut against the valve bridge and eliminate the clearance between the valve bridge and the hydraulic tappet.Type: GrantFiled: December 7, 2020Date of Patent: February 6, 2024Assignee: WEICHAI POWER CO., LTD.Inventors: Shenggang Guo, Fei Wang, Cheng Xu
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Patent number: 11888015Abstract: Disclosed is an X-ray sensor having an active detector region including detector diodes on its surface. The X-ray sensor further includes a junction termination surrounding the surface region including the detector diodes. The junction termination includes a guard arranged closest to the end of the surface region, a field stop outside the guard and at least two field limiting rings, FLRs arranged between the guard and the field stop. A first FLR is arranged at a distance ?1 from the guard selected from the interval [4 ?m; 12 ?m], a second FLR is arranged at a distance ?2 from the first FLR selected from the interval [6.5 ?m; 14 ?m], and wherein the distance ?2 is larger than the distance ?1. The proposed technology also provides a method for constructing such an X-ray sensor and an X-ray imaging system including an X-ray detector system that includes such X-ray sensor.Type: GrantFiled: May 14, 2019Date of Patent: January 30, 2024Assignee: Prismatic Sensors ABInventors: Mietek Bakowski Holtryd, Mats Danielsson, Cheng Xu
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Patent number: 11841242Abstract: Disclosed are a preprocessing method and device for distance transformation. The method includes: acquiring a first grid map; calculating a second parameter of a vehicle model; calculating a precision of a second grid map according to the second parameter of the vehicle model and a precision of the first grid map; calculating the numbers of rows and columns of the second grid map according to information on the first grid map, the precision of the second grid map and the second parameter of the vehicle model; determining for each cell of the second grid map a state value according to the numbers of obstacle cells within said each cell; and determining in the first grid map at least one cell requiring no processing, according to the state value. Therefore, during the distance transformation, the processing speed for determining the distance value of each cell is increased.Type: GrantFiled: March 30, 2021Date of Patent: December 12, 2023Assignee: BEIJING IDRIVERPLUS TECHNOLOGY CO., LTD.Inventors: Runlin He, Bo Yan, Cheng Xu, Fang Zhang, Xiaofei Li, Dezhao Zhang, Xiao Wang, Shuhao Huo
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Patent number: 11830809Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.Type: GrantFiled: March 25, 2020Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Ying Wang, Yikang Deng, Junnan Zhao, Andrew James Brown, Cheng Xu, Kaladhar Radhakrishnan
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Publication number: 20230369192Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Jonathan ROSCH, Wei-Lun JEN, Cheng XU, Liwei CHENG, Andrew BROWN, Yikang DENG
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Publication number: 20230352385Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.Type: ApplicationFiled: May 8, 2023Publication date: November 2, 2023Applicant: Tahoe Research, Ltd.Inventors: Yikang DENG, Ying WANG, Cheng XU, Chong ZHANG, Junnan ZHAO
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Publication number: 20230337466Abstract: A display substrate and a manufacture method thereof, and a display apparatus are provided. The base substrate includes a base substrate, the base substrate is provided with a plurality of pixels in an array, one pixel includes a plurality of sub-pixels, each sub-pixel includes a light-emitting device and a pixel circuit driving the light-emitting device to emit light, and the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor; the first electrode of the driving transistor receives a first power voltage; the second electrode of the driving transistor is connected to the light-emitting device; at least part of the plurality of sub-pixels includes a first via hole, and the first electrode of the data writing transistor is electrically connected to the gate electrode of the driving transistor and the active layer of the data writing transistor through the first via hole.Type: ApplicationFiled: March 30, 2021Publication date: October 19, 2023Inventors: Leilei CHENG, Cheng XU, Jie LIU, Chunjie XU
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Publication number: 20230332520Abstract: A rocker arm mechanism includes a rocker arm shaft, a rocker arm, a valve clearance adjuster, a valve train, and a control valve. The rocker arm is rotatably disposed on the rocker arm shaft. The valve train includes a valve bridge. The rocker arm is provided with a plunger chamber. The valve clearance adjuster includes a hydraulic tappet slidably disposed in the plunger chamber. The plunger chamber is supplied with oil through an oil supply passage. The control valve is configured to open or close the oil supply passage. When the control valve opens the oil supply passage, the hydraulic tappet can abut against the valve bridge and eliminate the clearance between the valve bridge and the hydraulic tappet.Type: ApplicationFiled: December 7, 2020Publication date: October 19, 2023Inventors: Shenggang GUO, Fei WANG, Cheng XU
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Patent number: 11769719Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.Type: GrantFiled: June 25, 2018Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Jonathan Rosch, Wei-Lun Jen, Cheng Xu, Liwei Cheng, Andrew Brown, Yikang Deng
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Patent number: 11768115Abstract: Methods, systems and devices of the present disclosure involve techniques for cancelling base resistance error otherwise present in remote temperature sensors such as remote diode temperature sensors. In one or more embodiments, measurement logic configured to determine a temperature of or near a remote temperature sensor may be configured to determine an error cancelling coefficient and to calculate a temperature value, at least in part, responsive to the error cancelling coefficient. In some cases, error cancelling coefficients may be determined using one or more calibration techniques.Type: GrantFiled: November 8, 2021Date of Patent: September 26, 2023Assignee: Microchip Technology IncorporatedInventors: Hyunsoo Yeom, Cheng Xu
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Patent number: 11761263Abstract: The present application provides a balance force component of a cordless window shade, which relates to the technical field of window shade components. A balance force component of a cordless window shade, comprising a windows shade tube, a core tube component is respectively provided at both ends inside the window shade tube, a deceleration component is respectively provided at the outer ends of the core tube component, and the outer ends of the deceleration components are respectively provided with a mounting component, the core tube component comprises an outer bracket, a number of clamping holes are equidistantly arranged on one side of the outer bracket, both sides of the outer wall of the outer bracket are provided with limiting grooves, and the outer ends of the inner wall of the outer bracket are provided with tooth grooves.Type: GrantFiled: January 13, 2023Date of Patent: September 19, 2023Inventor: Cheng Xu
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Patent number: 11735537Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.Type: GrantFiled: June 28, 2022Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
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Patent number: 11721677Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.Type: GrantFiled: December 27, 2018Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Chong Zhang, Cheng Xu, Junnan Zhao, Ying Wang, Meizi Jiao
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Publication number: 20230238368Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.Type: ApplicationFiled: March 30, 2023Publication date: July 27, 2023Inventors: Chong ZHANG, Cheng XU, Junnan ZHAO, Ying WANG, Meizi JIAO
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Patent number: 11705389Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.Type: GrantFiled: June 11, 2019Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Andrew J. Brown, Luke Garner, Liwei Cheng, Lauren Link, Cheng Xu, Ying Wang, Bin Zou, Chong Zhang
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Patent number: 11696407Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.Type: GrantFiled: December 22, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Chong Zhang, Ying Wang, Junnan Zhao, Cheng Xu, Yikang Deng
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Publication number: 20230209125Abstract: A method for displaying information is provided. The method includes: receiving a video data stream for displaying a first video related to a virtual space and recommending the virtual space; displaying the first video related to the virtual space based on the video data stream; and displaying recommendation information of the virtual space on the first video related to the virtual space, wherein the recommendation information is determined based on a live streaming goal of the virtual space, the live streaming goal indicating an effect to be achieved by live streaming.Type: ApplicationFiled: July 29, 2022Publication date: June 29, 2023Inventors: Yanting LIU, Kaijie CHEN, Yulin SONG, Cheng XU, Xiang LI, Ximing CHEN, Wenya WU