Patents by Inventor Cheng Yao
Cheng Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153958Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.Type: ApplicationFiled: January 7, 2024Publication date: May 9, 2024Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20240150354Abstract: The present application provides tricyclic urea compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.Type: ApplicationFiled: August 24, 2023Publication date: May 9, 2024Inventors: Yanran Ai, Onur Atasoylu, Yu Bai, Joseph Barbosa, David M. Burns, Daniel Levy, Brent Douty, Hao Feng, Leah C. Konkol, Cheng-Tsung Lai, Xun Liu, Song Mei, Jun Pan, Haisheng Wang, Liangxing Wu, Wenqing Yao, Eddy W. Yue
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Patent number: 11978768Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.Type: GrantFiled: June 8, 2023Date of Patent: May 7, 2024Assignee: Winbond Electronics Corp.Inventors: Tseng-Yao Pan, Chien-Hsiang Yu, Ching-Yung Wang, Cheng-Hong Wei, Ming-Tsang Wang
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Publication number: 20240145581Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
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Patent number: 11967594Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: GrantFiled: August 10, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 11966058Abstract: An ultra-thin lens for augmented reality (AR) display includes: a primary lens, an intermediate lens, and a secondary lens. After entering the primary lens, image light undergoes two total reflections, then enters the intermediate lens and is partially reflected, then is directed to a human eye through the intermediate lens and the primary lens. The secondary lens is configured on the other side of the intermediate lens, and environmental light is directed to the human eye through the secondary lens, the intermediate lens, and the primary lens. According to the ultra-thin lens, total reflection and light splitting functions of the image light are realized respectively through the primary lens and the intermediate lens, so that the entire lens has a thin and light profile.Type: GrantFiled: June 27, 2022Date of Patent: April 23, 2024Assignee: Beijing NED+AR Display Technology Co., Ltd.Inventors: Cheng Yao, Yuhao Xiao, Dewen Cheng
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Publication number: 20240120313Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
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Publication number: 20240119910Abstract: The invention provides an image capture device and an image processing method thereof. The image processing method includes the following steps. First, an image signal source is received by a receiving unit, wherein the image signal source has a plurality of image frames and plurality corresponding image information or plurality of corresponding variable refresh rate (VRR) related information. Next, it is determined whether the image signal source is a VRR signal, and a determination result is generated. A time stamp of each image frame is calculated according to the VRR-related information if the determination result is positive, wherein the time stamps correspond to a dynamic frame interval respectively. Next, the image frames are respectively converted into a corresponding output packet. Finally, the output packets are respectively integrated with their respective time stamps to generate a dynamic frame interval output packet.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Inventors: Yen-Cheng Yao, Chia-Jung Hsiao
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Publication number: 20240113345Abstract: A battery module and a short protection method thereof are provided. The battery module has a battery cell pack and a control circuit. The method includes: detecting a temperature of the battery cell pack as a battery cell temperature through the control circuit; determining whether the battery cell temperature shows a downward trend when the battery cell temperature is higher than a first predetermined temperature value; and deactivating the battery module when the battery cell temperature does not show the downward trend.Type: ApplicationFiled: May 23, 2023Publication date: April 4, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chunyen Lai, Yu-Cheng Shen, Chun Tsao, Chaochan Tan, Huichuan Lo, Wen-Che Chung, Ming Hung Yao
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Publication number: 20240105865Abstract: An optoelectronic device includes a first electrode, a second electrode that is spaced apart from the first electrode, an optoelectronic unit that is disposed between the first electrode and the second electrode, an insulating layer and a driving electrode. The optoelectronic unit includes an optoelectronic stack emitting or absorbing at least two wavelengths of light. The insulating layer is disposed on a lateral side of the optoelectronic stack that extends in a stacking direction of the optoelectronic stack. The driving electrode is disposed on the insulating layer at a location corresponding in position to the optoelectronic unit and is separated from the first and second electrodes.Type: ApplicationFiled: April 18, 2023Publication date: March 28, 2024Applicant: National Tsing Hua UniversityInventors: Cheng-Yao LO, Padmanabh Pundrikaksha PANCHAM, Yu-Xin ZENG, Chih-Liang PAN
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Publication number: 20240081184Abstract: The present invention relates to the field of water surface treatment, and in particular to a cleaning ship for water surface treatment for harvesting water plants. In order to solve the technical problems that the existing cleaning ship cannot adapt to the waters of different depths for harvesting water plants, and a hull has low load utilization rate for the collected water plants and affects the overall working efficiency and the fuel economy of the hull, the present invention provides a cleaning ship for water surface treatment for harvesting water plants, comprising a steel belt conveying mechanism, a driven shaft and the like. The steel belt conveying mechanism drives the driven shaft to rotate.Type: ApplicationFiled: September 1, 2023Publication date: March 14, 2024Inventors: Cheng Wu, Fengliang Dong, Xiaoyu Xue, Lei Gao, Peisong Wu, Yunfei Qian, Lijing Yao, Junyi Shi
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Publication number: 20240084487Abstract: A knitted component comprising two yarns, forming at least a heel region of an upper for an article of footwear, where one of the yarns comprises a thermoplastic material. The outer surface may include a fused area comprising a first thermoplastic yarn. The inner surface may be at least partially formed with a second yarn and may substantially exclude the thermoplastic material. There may be a transitional area including a reduced amount of thermoplastic material relative to a fused area. The knitted component may include a cushioning material between layers of the knit element.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Jessica Green, Chun-Ying Hsu, Jaroslav J. Lupinek, Darryl Matthews, William C. McFarland, II, Chun-Yao Tu, Yi-Ning Yang, Cheng-Ying Han
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Publication number: 20240083556Abstract: The present invention relates to the technical field of water surface waste treatment, and in particular to a water surface floater collecting ship. The technical problems are: picking up floaters with the cooperation of labors consumes manpower and causes disturbance of water surface, which makes the floaters float further away with water waves, and the odor emitted by the collected floating waste will pollute the environment and affect the salvage efficiency. The technical solution is: a water surface floater collecting ship, comprising a hull, a collecting system, etc.; the left part of the hull is connected with the collecting system used for collecting waste.Type: ApplicationFiled: September 1, 2023Publication date: March 14, 2024Inventors: Cheng Wu, Fengliang Dong, Xiaoyu Xue, Lei Gao, Peisong Wu, Yunfei Qian, Lijing Yao, Junyi Shi
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Patent number: 11929287Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.Type: GrantFiled: April 23, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Kuan-Ting Pan, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao
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Publication number: 20240080030Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.Type: ApplicationFiled: October 31, 2023Publication date: March 7, 2024Applicant: Silicon Motion, Inc.Inventors: Tien-Hsing Yao, Chun-Cheng Lee, Sheng-l Hsu
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Patent number: 11919908Abstract: The present application provides deazaguaine compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.Type: GrantFiled: December 20, 2021Date of Patent: March 5, 2024Assignee: Incyte CorporationInventors: Andrew W. Buesking, Onur Atasoylu, Cheng-Tsung Lai, Padmaja Polam, Liangxing Wu, Wenqing Yao
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Patent number: 11916122Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.Type: GrantFiled: July 8, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhi-Chang Lin, Kuan-Ting Pan, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao, Kuo-Cheng Chiang
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Patent number: 11908058Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for providing editable keyframe-based animation data for applying to a character to animate motion of the character in three-dimensional space. Three-dimensional motion data is constructed from two-dimensional videos. The three-dimensional motion data represents movement of people in the two-dimensional videos and includes, for each person, a root of a three-dimensional skeleton of the person. The three-dimensional skeleton comprises multiple three-dimensional poses of the person during at least a portion of frames of a video from the two-dimensional videos. The three-dimensional motion data is converted into editable keyframe-based animation data in three-dimensional space and provided to animate motion.Type: GrantFiled: February 16, 2022Date of Patent: February 20, 2024Assignee: Autodesk, Inc.Inventors: Fraser Anderson, George William Fitzmaurice, Cheng Yao Wang, Qian Zhou
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Patent number: 11871121Abstract: A video signal conversion method includes: receiving an input signal from a video source; extracting an image metadata from the input signal; determining whether the input signal corresponds to a high dynamic range (HDR) imaging format according to at least one format information of the image metadata and determining whether a video receiver supports the high dynamic range imaging format; in response to the input signal corresponding to the high dynamic range imaging format and the video receiver being not support the high dynamic range imaging format, generating a conversion command; receiving, by a video processor, the conversion command; converting, by the video processor, the input signal into an output signal corresponding to a standard dynamic range (SDR) imaging format according to the conversion command; sending, by the video processor, the output signal to the video receiver; and receiving by the video receiver, the output signal in SDR imaging format.Type: GrantFiled: July 14, 2021Date of Patent: January 9, 2024Assignee: AVerMedia TECHNOLOGIES, INC.Inventors: Wen-Chien Chang, Yen-Cheng Yao
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Publication number: 20230387736Abstract: A motor rotor is provided, comprising: a rotor core, comprising a plurality of metal parts and an inner hole of the rotor, the inner hole of the rotor passing through the rotor core, and the metal parts constituting a rotor metal total area ?Ametal; and a plurality of reluctance parts, disposed surrounding the inner hole of the rotor, each of the reluctance parts comprising at least one flux barrier, at least one of the flux barriers penetrating the rotor core, and the at least one of the flux barriers in each of the reluctance parts constituting a flux barrier total area ?Aair; wherein, the sum of ?Aair and ?Ametal being a rotor effective total area, and the ratio of ?Aair to the rotor effective total area being a flux barrier ratio KA, expressed as KA=?Aair/?Aair+?Ametal, and the flux barrier ratio KA satisfying the following relation: 0.25?KA?0.5.Type: ApplicationFiled: September 26, 2022Publication date: November 30, 2023Inventors: Cheng-Hu Chen, Yu-Cheng Yao, Ruey-Yue Lin