Abstract: A memory controller includes an interface circuit and a control circuit. The interface circuit is configured to communicate with a host device. When the control circuit finishes executing N commands from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer. The control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.

Abstract: A data backup method for backing up target data, through a driver module, from a first storage device to a second storage device is disclosed. The first storage device includes a first storage unit that stores the target data, and a first control unit that accesses the first storage unit based on a first logical-to-physical mapping table. The second storage device includes a second storage unit and a second control unit that accesses the second storage unit based on a second logical-to-physical mapping table. The method includes steps of: reading the target data from the first storage unit without accessing the first logical-to-physical mapping table and transmitting the target data to the driver module; transmitting the target data to the second control unit; and writing the target data to the second storage unit without accessing the second logical-to-physical mapping table.

Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.

Abstract: A data storage device includes a power line communication (PLC) circuit and a storage controller. The PLC circuit is coupled to a power line. The storage controller is coupled to the PLC circuit. The storage controller is configured to access a plurality of memory block. The PLC circuit is configured to carry at least one signal outputted from the storage controller on the power line, in order to transmit the at least one signal to an external device such that an operational state of the data storage device can be debugged/monitored.

Abstract: A memory controller includes: an interface configured to operably communicate with a host device; a temperature detecting circuit configured to operably detect an ambient temperature, wherein when the ambient temperature is beyond a predetermined temperature range, the temperature detecting circuit generates a control signal; and a processing circuit coupled to the interface and the temperature detecting circuit, for selecting one of a plurality of data program schemes to program data into a first storage block of a flash memory according to the control signal.

Abstract: An electronic device includes: a storage device containing a target block having multiple word lines and multiple bit lines; a transmission interface configured to operably receive data to be written into the storage device; and a controller circuit including: an access circuit; and a flash memory control circuit configured to operably control the access circuit to write a first data into one or more pages connected with a first word line in the target block using a first program scheme, and to operably control the access circuit to write a second data into one or more pages connected with a second word line in the target block using a second program scheme, so that the first data and the second data are stored in the target block at the same time.

Abstract: This invention discovers a purification method for isolating an extract containing chlorosesamone from roots of genus Sesamum plants, and its application. In this invention, D2 fraction containing chlorosesamone is obtained through an extraction step and a separation step. Then, through further purification step, chlorosesamone is obtained. In the experiment of this invention, D2 fraction or chlorosesamone extracted from roots of Sesamum indicum, a plant of genus Sesamum, can be used for the anticancer treatment for cancer cells of breast, liver, blood and lung.

Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.

Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple type

Abstract: A heat dissipation device control method for dissipating heat from an electronic element without self-heat-dissipation function in an electronic device. The method comprises: detecting a first temperature of the electronic element; and controlling the fan of the peripheral element located around the electronic element when the first temperature exceeds the first upper temperature threshold to dissipate the heat from the electronic element.

Abstract: A memory control device includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and configured to select a first memory block from the memory blocks and program data into the first memory block. When the memory control device is deactivated and re-activated, the controller is further configured to read a voltage distribution of the first memory block to determine a deactivation interval, and determine a reference time according to the deactivation interval and an initial time, and the voltage distribution of the first memory block correspond to the data.

Abstract: The production system of chlorine dioxide solution includes a water storage device, an electrolyte storage device, an electrolytic device, a reaction device, a storage device, a cooling device, and a cleaning device. These devices jointly work together to manufacture chlorine dioxide solution systematically and in mass production.

Abstract: A method for generating a security feature of a flash memory includes determining a memory block from a plurality of memory blocks in the flash memory; erasing data of the determined memory block of the flash memory; providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; and establishing a security feature based on the plurality of corresponding threshold voltages.

Abstract: A data storage device includes a power line communication (PLC) circuit and a storage controller. The PLC circuit is coupled to a power line. The storage controller is coupled to the PLC circuit. The storage controller is configured to access a plurality of memory block. The PLC circuit is configured to carry at least one signal outputted from the storage controller on the power line, in order to transmit the at least one signal to an external device such that an operational state of the data storage device can be debugged/monitored.

Abstract: A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit. The voltage supply circuit supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is configured to control an operation of the flash memory. The current sensing circuit is configured to measure the current consumed by the flash memory during its operation, and output a current value. The processor is configured to output a control signal based on the current value. Therefore, the flash memory controller can instantly obtain a current value consumed during the operation of flash memory, and determine, based on the current value, whether the flash memory runs normally. A storage apparatus having the flash memory controller can instantly determine whether the flash memory runs normally.

Abstract: A data storage device includes a power line communication (PLC) circuit and a storage controller. The PLC circuit is coupled to a power line. The storage controller is coupled to the PLC circuit. The storage controller is configured to access a plurality of memory block. The PLC circuit is configured to carry at least one signal outputted from the storage controller on the power line, in order to transmit the at least one signal to an external device such that an operational state of the data storage device can be debugged/monitored.

Abstract: A method for generating a security feature of a flash memory includes determining a memory block from a plurality of memory blocks in the flash memory; erasing data of the determined memory block of the flash memory; providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; and establishing a security feature based on the plurality of corresponding threshold voltages.

Abstract: A method for generating a random number, applied in a random number generator coupled to a flash memory is disclosed. the method comprises: selecting a plurality of cells from the flash memory; initializing the selecting cells of the flash memory; programming the selecting cells to obtain a plurality of first potential values of the selecting cells; re-initializing the selecting cells of the flash memory; re-programming the selecting cells to obtain a plurality of second potential values of the selecting cells; and processing the first potential values and the second potential values according to a predetermined algorithm to generating the random number.

Abstract: A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit. The voltage supply circuit supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is configured to control an operation of the flash memory. The current sensing circuit is configured to measure the current consumed by the flash memory during its operation, and output a current value. The processor is configured to output a control signal based on the current value. Therefore, the flash memory controller can instantly obtain a current value consumed during the operation of flash memory, and determine, based on the current value, whether the flash memory runs normally. A storage apparatus having the flash memory controller can instantly determine whether the flash memory runs normally.

Abstract: A memory control device includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and configured to select a first memory block from the memory blocks and program data into the first memory block. When the memory control device is deactivated and re-activated, the controller is further configured to read a voltage distribution of the first memory block to determine a deactivation interval, and determine a reference time according to the deactivation interval and an initial time, and the voltage distribution of the first memory block correspond to the data.