Abstract: A method for forming an under bump metal, comprising the following steps. A semiconductor structure is provided having an exposed I/O pad. A patterned passivation layer is formed over the semiconductor structure, the patterned passivation layer having an opening exposing a first portion of the I/O pad. A dry film resistor (DFR) layer is laminated, exposed and developed to form a patterned dry film resistor (DFR) layer over the patterned passivation layer. The patterned dry film resistor (DFR) layer having an opening exposing a second portion of the I/O pad. The patterned dry film resistor (DFR) layer opening having opposing side walls with a predetermined profile with an undercut. A metal layer is formed over the patterned dry film resistor (DFR) layer, the exposed third portion of the I/O pad, and over at least a portion of the opposing side walls of the patterned dry film resistor (DFR) layer opening.

Abstract: Within a method for fabricating an microelectronic fabrication there is first provided a substrate employed within an optoelectronic microelectronic fabrication, where the substrate comprises an optoelectronic microelectronic device which is in electrical communication with a bond pad formed over the substrate. There is then processed, when fabricating the substrate to form the optoelectronic microelectronic fabrication, the substrate in the absence of optoelectronically transducable radiation, in order to attenuate corrosion of the bond pad. The method is particularly useful for forming a color filter sensor image array optoelectronic microelectronic fabrication comprising multiple photoresist based patterned colored filter layers.

Abstract: A method for developing a semiconductor device low resistance electrical contact is described. In this process a gate oxide layer followed by a polysilicon layer is deposited on the semiconductor substrate in proximity to the device contact area. It is subsequently patterned with photoresist and etched to produce the desired gate structure. This is followed by a deposited layer of silicon dioxide or silicon nitride (SIN) which is appropriately patterned and etched to form gate isolation spacers. Then a nominal 300 Å layer of silicon nitride (SIN) is deposited followed by a layer of tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG). The contact area is defined by photolithography, and the passivation layers are etched either by a dry etch such as a RIE process, or a combination of a wet BOE process followed by a dry etch, to form the metal contact holes.

Abstract: A metal code process for a read-only memory (ROM) combines the alignment dip back process (to reduce the polyoxide thickness over the gate electrode and to protect the field oxide) with a double charge implant approach to provide the function of a depletion mode ROM cell. The alignment dip back process also avoids leakage current problems. A stable depletion mode device character is achieved by implant step energies greater than 150 keV.