Patents by Inventor Cheng Yu

Cheng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379429
    Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes: forming a carrier; forming a sacrificial layer on the carrier; forming a through via on the sacrificial layer, wherein the through via includes a seed layer and a metal feature; disposing a die on the sacrificial layer, wherein the die has a plurality of metal pillars disposed at a side of the die facing away from the sacrificial layer; forming a molding compound on the sacrificial layer to cover and surround the die and the through via; removing a portion of the molding compound and a portion of the through via above the die to expose the metal feature of the through via; and removing the carrier and sacrificial layer to expose the seed layer of the through via.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: JING-CHENG LIN, YING-CHING SHIH, PU WANG, CHEN-HUA YU
  • Publication number: 20240379422
    Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Sung-Li WANG, Chih-Hao WANG
  • Publication number: 20240379782
    Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Wei Hsu, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240379418
    Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN
  • Publication number: 20240379775
    Abstract: A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240379799
    Abstract: A semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. The gate structure wraps around the semiconductor layer. The source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. The backside dielectric cap is disposed under and in direct contact with the gate structure. The inner spacer is in direct contact with the gate structure and the backside dielectric cap.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Ting Chung, Hou-Yu Chen, Ching-Wei Tsai
  • Publication number: 20240379796
    Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
  • Patent number: 12141060
    Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: dividing a GC operation into a plurality of partial GC operations; determining a default partial GC operation time period for each partial GC operation; determining a partial GC intensity according to at least a basic adjustment factor and an amplification factor; determining the basic adjustment factor according to a type of one or more source blocks corresponding to the GC operation; determining the amplification factor according to a percentage of invalid pages in the one or more source blocks corresponding to the GC operation; and performing the plurality of partial GC operations according to the partial GC intensity and the default partial GC operation time period.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: November 12, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Chia-Chi Liang, Cheng-Yu Tsai
  • Patent number: 12142637
    Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yu Lin, Yi-Lin Fan, Hui-Zhong Zhuang, Sheng-Hsiung Chen, Jerry Chang Jui Kao, Xiangdong Chen
  • Patent number: 12140674
    Abstract: A tracking device including an image sensor, a light source and a processor is provided. The image sensor senses reflected light or scattered light formed by the light source illuminating a work surface. The processor calculates a trace of the tracking device according to one of the reflected light and the scattered light that generates more apparent image features so as to increase the adaptable work surfaces.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: November 12, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Hui-Hsuan Chen, Cheng-Lin Yang, Tzu-Yu Chen
  • Patent number: 12142624
    Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface opposite to the first surface in a vertical direction, a first isolation structure disposed in the semiconductor substrate for defining pixel regions, a visible light detection structure, an infrared light detection structure, and a reflective layer. The visible light detection structure and the infrared light detection structure are disposed within the same pixel region. The visible light detection structure includes a first portion disposed between the second surface and the infrared light detection structure in the vertical direction and a second portion disposed between the infrared light detection structure and the first isolation structure in a horizontal direction. The infrared light detection structure is disposed between the reflective layer and the first portion in the vertical direction. The second portion is not sandwiched between the reflective layer and the second surface in the vertical direction.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: November 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Cheng-Yu Hsieh
  • Publication number: 20240368472
    Abstract: A surfactant composition includes 60 wt % or greater of a surfactant based on a total weight of the surfactant composition and 0.01 wt % to 5 wt % of a hydroxyl amine having structure (I) based on the total weight of the surfactant composition, wherein R1, R2 and R3 of Structure (I) are independently selected from the group consisting of H, an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons, and R4 of Structure (I) is selected from the group consisting of an alkanolamine, or a hydroxyl alkyl group with linear or branched carbon chain having from 1 to 8 carbons.
    Type: Application
    Filed: October 6, 2021
    Publication date: November 7, 2024
    Inventors: Cheng Shen, Haiying Li, Shaoguang Feng, Jian Zou, Wanglin Yu
  • Publication number: 20240372004
    Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Feng-Cheng YANG, Chung-Te LIN
  • Publication number: 20240371895
    Abstract: A method for forming an image sensor package is provided. An image sensor chip is formed over a package substrate. A protection layer is formed overlying the image sensor chip. The protection layer has a planar top surface and a bottom surface lining and contacting structures under the protection layer. An opening is formed into the protection layer and spaced around a periphery of the image sensor chip. A light shielding material is filled in the opening to form an on-wafer shield structure having a sidewall directly contact the protection layer.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Publication number: 20240373651
    Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien WU, Xinyu BAO, Hengyuan Lee, Ying-Yu Chen
  • Publication number: 20240371773
    Abstract: Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, an isolation layer disposed over the gate electrode layer, a first sidewall spacer in contact with the gate dielectric layer, and a liner layer having a first portion disposed between the isolation layer and the gate electrode layer and a second portion in contact with the first sidewall spacer.
    Type: Application
    Filed: July 13, 2024
    Publication date: November 7, 2024
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20240373650
    Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: HUI-HSIEN WEI, YEN-CHUNG HO, CHIA-JUNG YU, YONG-JIE WU, PIN-CHENG HSU
  • Publication number: 20240373646
    Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Inventors: Hui-Hsien WEI, Yen-Chung HO, Chia-Jung YU, Yong-Jie WU, Pin-Cheng HSU
  • Publication number: 20240370367
    Abstract: A method for performing garbage collection (GC) management of a memory device with aid of block classification and associated apparatus are provided. The method may include: utilizing a memory controller to divide at least one portion of blocks among a plurality of blocks into multiple first blocks belonging to at least one first type in a first area and multiple second blocks belonging to at least one second type in a second area; utilizing the memory controller to receive a first command from a host device through a transmission interface circuit within the memory controller; and during writing data in response to the first command, performing a foreground GC procedure to control the memory device to perform GC before completing at least one writing operation corresponding to the first command, for controlling priority of releasing storage space of the second area to be higher than that of the first area.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 7, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Cheng-Yu Tsai
  • Patent number: 12136660
    Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ming Lin, Han-Yu Lin, Wei-Yen Woon, Mrunal Abhijith Khaderbad