Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.

Abstract: A memory device and method of making the same, the memory device including bit lines disposed on a substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.

Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a dielectric layer and a transistor. The transistor is at least partially disposed in the dielectric layer. The transistor includes a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a semiconductor layer. The gate dielectric layer is disposed over the gate electrode. The source electrode and the drain electrode are disposed over the gate dielectric layer and contact the gate dielectric layer. The semiconductor layer is disposed over the gate dielectric layer.

Abstract: Using a large language model to comply with a user request. The large language model receives tool documentation for each of one or more tools, and analyzes the tool documentation for each of the one or more tools to determine, for each tool, one or more tasks that the tool is operable to perform. Upon receiving a request from a user, the large language model generates a plan for complying with the request by using one or more of the tools, the plan including performance of one or more of the tasks.

Abstract: The present disclosure provides a light-emitting device and a manufacturing method thereof, a taillight and a vehicle. The light-emitting device includes at least one light-emitting element located on one side of a backplane, wherein a wavelength of a first light emitted by each light-emitting element is 500 nm to 580 nm; a wavelength conversion layer located on one side of the at least one light-emitting element away from the backplane and configured to emit a second light with a different color from the first light under the excitation of the first light; and a first optical structure located on one side of the wavelength conversion layer away from the backplane, and including one or more optical elements, each of which is configured to focus the second light along a direction perpendicular to the backplane.

Abstract: A hypochlorous acid preparation system is provided. The hypochlorous acid preparation system includes: a hypochlorous acid preparation apparatus comprising: a first inlet, wherein sulfuric acid collected from a clean room located in a semiconductor fabrication plant enters the hypochlorous acid preparation apparatus through the first inlet; a second inlet, wherein sodium hypochlorite solution enters the hypochlorous acid preparation apparatus through the second inlet; a third inlet, wherein deionized water enters the hypochlorous acid preparation apparatus through the third inlet; and an outlet, wherein hypochlorous acid is produced in situ by mixing the sulfuric acid, the sodium hypochlorite solution, and the deionized water and exits the hypochlorous acid preparation apparatus through the outlet.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: A fuel cell interconnect includes fuel ribs disposed on a first side of the interconnect and a least partially defining fuel channels, and air ribs disposed on an opposing second side of the interconnect and at least partially defining air channels. The fuel channels include central fuel channels disposed in a central fuel field and peripheral fuel channels disposed in peripheral fuel fields disposed on opposing sides of the central fuel field. The air channels include central air channels disposed in a central air field and peripheral air channels disposed in peripheral air fields disposed on opposing sides of the central air field. At least one of the central fuel channels or the central air channels has at least one of a different cross-sectional area or length than at least one of the respective peripheral fuel channels or the respective peripheral air channels.

Abstract: Additive-polymer precursor materials for filaments (e.g., for three-dimensional (3D) printing) are provided, as well as methods of fabricating and using the same. One or more two-dimensional (2D) additive materials (e.g., nano materials, such as nanosheets) can be mixed with a polymer base to give an additive-polymer precursor composite material. The additive material can be dissolved in a first solvent to give an additive solution, and the polymer can be dissolved in a second solvent to give a polymer base. The additive solution can be mixed with the polymer base to give a mixed solution. Solvent casting can then be performed on the mixed solution to evaporate the solvent(s) and give the additive-polymer precursor composite material, which can have a layered structure.

Abstract: An image interpolation method comprises applying a filter to an RGBIR image to generate a LUMA image; calculating two gradients according to the LUMA image; and interpolating a missing pixel between two pixels in the RGBIR image according to the two gradients. Wherein each gradient corresponding to two LUMA pixels in the LUMA image. An image fusion method comprises applying a filter to an RGBIR image to generate a LUMA image; obtaining an R-image, a G-image, a B-image and an IR image according to the RGBIR image; and generating a fusion image according to the R-image, G-image, B-image, the IR image and the LUMA image.

Abstract: A tracking device including an image sensor, a light source and a processor is provided. The image sensor senses reflected light or scattered light formed by the light source illuminating a work surface. The processor calculates a trace of the tracking device according to one of the reflected light and the scattered light that generates more apparent image features so as to increase the adaptable work surfaces.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The weight average molecular weight of the second fluoropolymer ranges from 630000 g/mol to 1100000 g/mol. The conductive filler is dispersed in the polymer matrix, thereby forming an electrically conductive path in the heat-sensitive layer.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The first fluoropolymer includes a first melting point, and the second fluoropolymer has a second melting point lower than the first melting point. The difference between the first melting point and the second melting point is smaller than 14° C. The second fluoropolymer has a second melt flow index ranging from 0.4 g/10 min to 0.7 g/10 min.

Abstract: An over-current protection device includes an electrode layer and a heat-sensitive layer. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic, and is laminated between a top metal layer and a bottom metal layer of the electrode layer. The heat-sensitive layer includes a polymer matrix and a conductive filler. The polymer matrix includes a first fluoropolymer and a second fluoropolymer. The first fluoropolymer has a first volume and a first melt flow index, and the second fluoropolymer has a second volume and a second melt flow index. The second melt flow index ranges from 0.4 g/10 min to 0.7 g/10 min and is lower than the first melt flow index, and a volume ratio by dividing the second volume by the first volume ranges from 0.4 to 0.6.