Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of striped selective gates perpendicular to the striped active area are disposed on the gate oxide layer and the isolation region. A pair of islanded floating gates are disposed on the gate oxide layer at the active area, with a gap between the pair of floating gates and the pair of selective gates. A striped p-well is disposed in the deep n-well between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the p-well, and connected to each other through the deep n-well. A drain is disposed in the p-well between the pair of selective gates.

Abstract: A flash memory structure is provided. The flash memory structure includes a P-type substrate, a deep N-well set up within the P-type substrate, a P-well set up within the deep N-well, a pair of gate structures set up over the substrate, a select gate set up between the pair of gate structure and N-type source/drain regions in the P-well on each side of the gate structure. Since each pair of neighboring gate structure uses a common gate, the level of integration of device can be increased.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A NAND flash memory cell row and the manufacturing method thereof are provided. The memory cell row includes first and second stacked gate structures, control and floating gates,an intergate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. Each of the first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of the second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is disposed between each of the first stacked gate structures, and between each of the second stacked gate structures and the adjacent first stacked gate structure. The floating gate is disposed between the control gate and the substrate and has a concave surface with a sharp edge. The inter-gate dielectric layer is disposed between the control and floating gates. The tunnel oxide is disposed between the floating gate and the substrate.

Abstract: A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and then etched to form two control gates. The control gates are oxidized to form a plurality of second oxide layers on surfaces of the control gates and aside the control gates. The dielectric layer and the floating gate layer are etched by utilizing the second oxide layers as a mask to form a floating gate underneath each of the control gates. A source is formed between the floating gates. The floating gates and the substrate are oxidized to form a plurality of first oxide layers aside the floating gates and form a third oxide layer on a surface of the source.

Abstract: A NAND flash memory cell array including a plurality of memory cell row is provided. Each of memory cell row includes a plurality of memory cells disposed between first selecting transistor and second selecting transistor connected in series. Each memory cell has a tunneling dielectric layer, a floating gate, an inter-gate dielectric, a control gate and source/drain regions. An erase gate is disposed between two adjacent memory cells. A plurality of word lines serve to connect the memory cells in rows. A source line serves to connect the source region of the first transistor in a row, whereas a plurality of bit lines serve to connect the drain region of second transistor in a row. A first selecting gate line and a second selecting gate line serve to connect the gate of the first transistor in a row and the gate of second transistor in a row respectively. A plurality of erase gate lines is connected to the erase gates in a row.

Abstract: A method of manufacturing a flash memory is provided. First, a substrate with a first gate structure and a second gate structure thereon is provided. The first gate structure and the second gate structure each comprises of a dielectric layer, a first conductive layer and a cap layer. A tunneling oxide layer is formed over the substrate and then a first spacer is formed on the sidewall of the first conductive layer. Thereafter, a second conductive layer is formed on one side designated for forming a source region of the sidewalls of the first gate structure and the second gate structure. Then, the source region is formed in the substrate in the designated area. Next, an inter-gate dielectric layer is formed over the second conductive layer and then an insulating layer is formed over the source region. After forming a third conductive layer over the area between the first gate structure and the second gate structure, a drain region is formed in the substrate.

Abstract: A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.

Abstract: A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.

Abstract: A flash memory includes a substrate, at least a source and two drains formed in the substrate, and the source located between the drains, two tunnel oxide layers formed on the substrate between each drain and the source, a floating gate formed on each of the tunnel oxide layers, a plurality of first oxide layers formed aside each of the floating gates, a dielectric layer formed on each of the floating gates, a control gate formed on each of the dielectric layers, a plurality of second oxide layers formed on surfaces of the control gates and extending toward both sides of the control gates, a lateral width of each second oxide layer being larger than a lateral width of each oxide layer, a third oxide layer formed on the source, and an erasing gate formed on the third oxide layer and located between the floating gates.

Abstract: A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.

Abstract: A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer located on the p-type shallow well, a floating gate on one sidewall of the control gate and over the substrate, a tunnel oxide layer between the control gate and the floating gate and between the floating gate and the substrate, a drain and a common source disposed beneath each side of the control gate in the substrate, wherein the depth of the drain and the common source are larger than the depth of the shallow p-type well, a pocket p-type well in the substrate around the drain and electrically connecting with the shallow p-type well.

Abstract: A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.

Abstract: A flash memory cell structure is provided. The flash memory cell includes a substrate, a gate structure, a source region, an erase gate, an erase gate dielectric layer, a select gate, a select gate dielectric layer and a drain region. The gate structure is set up over the substrate. The gate structure includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a spacer. The source region is formed in the substrate on one side of the gate structure. The erase gate is formed over the source region on one side of the gate structure. The erase gate dielectric layer is formed between the erase gate and the source region. The select gate is set up on another side of the gate structure. The select gate dielectric layer is formed between the select gate and the substrate. The drain region is formed in the substrate on one side of the select gate.

Abstract: A process for forming a high voltage oxide (HV) and a select gate poly for a split-gate flash memory is disclosed. The general difficulty of forming oxides of two different thicknesses for two different areas on the same substrate is alleviated by forming an HV oxide layer over the entire substrate just prior to the forming of the control gate of a cell area after the forming of a gate oxide layer over the peripheral area of the substrate. At an immediate subsequent step, a peripheral gate is formed over the HV oxide over the peripheral area, and, as a final step, the forming of the control gate, or the select gate of the cell area follows next.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.

Abstract: A flash memory structure is provided. The flash memory structure includes a P-type substrate, a deep N-well set up within the P-type substrate, a P-well set up within the deep N-well, a pair of gate structures set up over the substrate, a select gate set up between the pair of gate structure and N-type source/drain regions in the P-well on each side of the gate structure. Since each pair of neighboring gate structure uses a common gate, the level of integration of device can be increased.