Abstract: A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer located on the p-type shallow well, a floating gate on one sidewall of the control gate and over the substrate, a tunnel oxide layer between the control gate and the floating gate and between the floating gate and the substrate, a drain and a common source disposed beneath each side of the control gate in the substrate, wherein the depth of the drain and the common source are larger than the depth of the shallow p-type well, a pocket p-type well in the substrate around the drain and electrically connecting with the shallow p-type well.

Abstract: A flash memory device with selective gate within a substrate and method of fabricating the same. The flash memory device comprises a substrate with a floating gate disposed thereon. A wordline extends along a first direction and overlies the floating gate and the adjacent substrate thereof. A trench is disposed in the substrate adjacent to one side of the wordline. A selective gate is vertically disposed in the trench, partially covering the floating gate. A source region is disposed in the substrate adjacent to the other side of the wordline and a drain region is disposed in the substrate beneath the selective gate.

Abstract: A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.

Abstract: A flash memory includes a substrate, at least a source and two drains formed in the substrate, and the source located between the drains, two tunnel oxide layers formed on the substrate between each drain and the source, a floating gate formed on each of the tunnel oxide layers, a plurality of first oxide layers formed aside each of the floating gates, a dielectric layer formed on each of the floating gates, a control gate formed on each of the dielectric layers, a plurality of second oxide layers formed on surfaces of the control gates and extending toward both sides of the control gates, a lateral width of each second oxide layer being larger than a lateral width of each oxide layer, a third oxide layer formed on the source, and an erasing gate formed on the third oxide layer and located between the floating gates.

Abstract: A method of manufacturing a flash memory is provided. First, a substrate with a first gate structure and a second gate structure thereon is provided. The first gate structure and the second gate structure each comprises of a dielectric layer, a first conductive layer and a cap layer. A tunneling oxide layer is formed over the substrate and then a first spacer is formed on the sidewall of the first conductive layer. Thereafter, a second conductive layer is formed on one side designated for forming a source region of the sidewalls of the first gate structure and the second gate structure. Then, the source region is formed in the substrate in the designated area. Next, an inter-gate dielectric layer is formed over the second conductive layer and then an insulating layer is formed over the source region. After forming a third conductive layer over the area between the first gate structure and the second gate structure, a drain region is formed in the substrate.

Abstract: A flash memory structure is provided. The flash memory structure includes a P-type substrate, a deep N-well set up within the P-type substrate, a P-well set up within the deep N-well, a pair of gate structures set up over the substrate, a select gate set up between the pair of gate structure and N-type source/drain regions in the P-well on each side of the gate structure. Since each pair of neighboring gate structure uses a common gate, the level of integration of device can be increased.

Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

Abstract: A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer located on the p-type shallow well, a floating gate on one sidewall of the control gate and over the substrate, a tunnel oxide layer between the control gate and the floating gate and between the floating gate and the substrate, a drain and a common source disposed beneath each side of the control gate in the substrate, wherein the depth of the drain and the common source are larger than the depth of the shallow p-type well, a pocket p-type well in the substrate around the drain and electrically connecting with the shallow p-type well.

Abstract: A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.

Abstract: A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of striped selective gates perpendicular to the striped active area are disposed on the gate oxide layer and the isolation region. A pair of islanded floating gates are disposed on the gate oxide layer at the active area, with a gap between the pair of floating gates and the pair of selective gates. A striped p-well is disposed in the deep n-well between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the p-well, and connected to each other through the deep n-well. Adrain is disposed in the p-well between the pair of selective gates.

Abstract: A manufacturing method of flash memory. A substrate is provided, on which a gate structure is formed. A first spacer is formed on the sidewalls of the gate structure. A source region is formed in the substrate at one side of the gate structure. A first conductive layer and a sacrificial layer are formed on the substrate. The first conductive layer and the sacrificial layer are removed until the gate structure is exposed. A thermal oxidation process is performed to form a mask layer on the first conductive layer and the gate structure. The sacrificial layer remaining on the first conductive layer is removed, and the first conductive layer is etched with a square shape. The mask layer is removed, and a second spacer is formed on the sidewalls of the second conductive layer. A drain region is formed in the substrate at one side of the conductive layer.

Abstract: A manufacturing method of flash memory. A substrate is provided, on which a gate structure is formed. A first spacer is formed on the sidewalls of the gate structure. A source region is formed in the substrate at one side of the gate structure. A first conductive layer and a sacrificial layer are formed on the substrate. The first conductive layer and the sacrificial layer are removed until the gate structure is exposed. A thermal oxidation process is performed to form a mask layer on the first conductive layer and the gate structure. The sacrificial layer remaining on the first conductive layer is removed, and the first conductive layer is etched with a square shape. The mask layer is removed, and a second spacer is formed on the sidewalls of the second conductive layer. A drain region is formed in the substrate at one side of the conductive layer.

Abstract: A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.

Abstract: A split-gate flash memory structure. The flash memory structure mainly includes a substrate, a control gate over the substrate and a floating gate between the substrate and the control gate. A first side of the floating gate and the control gate are aligned. A second side of the floating gate protrudes beyond the control gate and has a corner with a sharp profile. The structure further includes spacers on the sidewalls of the control gate and the floating gate, a source region in the substrate on the first side of the floating gate, a drain region in the substrate on the second side of the floating gate and a select gate in the substrate between the spacers and the drain region. The sharp corner on the floating gate generates a higher electric field that speeds the erasure of data from the flash memory.

Abstract: A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of striped selective gates perpendicular to the striped active area are disposed on the gate oxide layer and the isolation region. A pair of islanded floating gates are disposed on the gate oxide layer at the active area, with a gap between the pair of floating gates and the pair of selective gates. A striped p-well is disposed in the deep n-well between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the p-well, and connected to each other through the deep n-well. A drain is disposed in the p-well between the pair of selective gates.

Abstract: A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of striped selective gates perpendicular to the striped active area are disposed on the gate oxide layer and the isolation region. A pair of islanded floating gates are disposed on the gate oxide layer at the active area, with a gap between the pair of floating gates and the pair of selective gates. A striped p-well is disposed in the deep n-well between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the p-well, and connected to each other through the deep n-well. A drain is disposed in the p-well between the pair of selective gates.

Abstract: A method of fabricating a flash memory is provided. A pad layer and a mask layer are formed over the substrate, and then the mask layer is patterned for forming an opening therein. The pad layer exposed by the opening is removed. After a tunneling dielectric layer is formed on the bottom of the opening, a floating gate is formed on the sidewall of the opening. The top of the floating gate is lower than a surface of the mask layer. A source region is formed in the substrate. Thereafter, an inter-gate dielectric layer is formed in the opening and a control gate is filled in the opening. The mask layer is removed and then a gate dielectric layer is formed on the substrate and a spacer is formed on the sidewall of the floating gate and the control gate. A select gate is formed on the sidewall of the spacer. A drain region is formed in the substrate on one side of the select gate.

Abstract: A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.

Abstract: A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.

Abstract: A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a sacrificial oxide against which the polysilicon sidewall is formed. An etch stop, such as a gate oxide is formed alongside the step. A polysilicon layer is deposited over the step followed by a silicon nitride layer. Next a flowable layer is deposited and cured. In a first embodiment the flowable layer is deposited to completely cover the polysilicon layer. Next the wafer is planarized to exposed the polysilicon layer over the high part of the step an to a level wherein the polysilicon/silicon nitride interface is driven away from the step to a distance which determines the final width of the final sidewall structure. The residual flowable layer is then removed and a silicon oxide hardmask is grown over the exposed polysilicon.