Patents by Inventor Cheng-Yuan KUNG

Cheng-Yuan KUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111165
    Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao-Kai HUNG, Chien-Wei CHANG, Ya-Chen SHIH, Hung-Jung TU, Hung-Yi LIN, Cheng-Yuan KUNG
  • Publication number: 20210090965
    Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Hsu-Chiang SHIH, Cheng-Yuan KUNG, Hung-Yi LIN
  • Patent number: 10903907
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Yuan Kung, Hung-Yi Lin
  • Publication number: 20200035654
    Abstract: A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 30, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Cheng-Yuan KUNG
  • Publication number: 20190393297
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Chien-Hua CHEN, Teck-Chong LEE, Hung-Yi LIN, Pao-Nan LEE, Hsin Hsiang WANG, Min-Tzu HSU, Po-Hao CHEN
  • Patent number: 10490341
    Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 26, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Teck-Chong Lee, Sheng-Chi Hsieh, Chien-Hua Chen
  • Patent number: 10475718
    Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Hung-Yi Lin, Cheng-Yuan Kung, Teck-Chong Lee, Shiuan-Yu Lin
  • Patent number: 10472228
    Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Cheng-Yuan Kung, Che-Hau Huang, Chin-Cheng Kuo
  • Patent number: 10475734
    Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Cheng-Yuan Kung
  • Publication number: 20190181082
    Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.
    Type: Application
    Filed: February 15, 2019
    Publication date: June 13, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Sheng-Chi HSIEH, Cheng-Yuan KUNG
  • Publication number: 20190055118
    Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Cheng-Yuan KUNG, Che-Hau HUANG, Chin-Cheng KUO
  • Publication number: 20190057809
    Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Teck-Chong LEE, Sheng-Chi HSIEH, Chien-Hua CHEN
  • Patent number: 10211137
    Abstract: A method for manufacturing a semiconductor device package includes providing a substrate having a first surface and a second surface opposite to the first surface; disposing a passive component layer on the first surface of the substrate; after disposing the passive component layer, forming at least one via in the substrate, wherein the via penetrates the substrate and the passive component layer; and disposing a conductive layer on the passive component layer and filling the via with the conductive layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Cheng-Yuan Kung
  • Publication number: 20180358291
    Abstract: A method for manufacturing a semiconductor device package includes providing a substrate having a first surface and a second surface opposite to the first surface; disposing a passive component layer on the first surface of the substrate; after disposing the passive component layer, forming at least one via in the substrate, wherein the via penetrates the substrate and the passive component layer; and disposing a conductive layer on the passive component layer and filling the via with the conductive layer.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Sheng-Chi HSIEH, Cheng-Yuan KUNG
  • Publication number: 20180337164
    Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Inventors: Chien-Hua CHEN, Hung-Yi LIN, Cheng-Yuan KUNG, Teck-Chong LEE, Shiuan-Yu LIN
  • Publication number: 20180247904
    Abstract: The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.
    Type: Application
    Filed: February 24, 2017
    Publication date: August 30, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Chi HSIEH, Hung-Yi LIN, Cheng-Yuan KUNG, Pao-Nan LEE, Chien-Hua CHEN