Patents by Inventor Cheng-Yuan KUNG
Cheng-Yuan KUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220384309Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Chin-Cheng KUO, Wu Chou HSU
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Patent number: 11508668Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.Type: GrantFiled: December 3, 2020Date of Patent: November 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
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Patent number: 11502067Abstract: A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.Type: GrantFiled: July 22, 2019Date of Patent: November 15, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Cheng-Yuan Kung
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Publication number: 20220293538Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.Type: ApplicationFiled: May 31, 2022Publication date: September 15, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
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Publication number: 20220181268Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Meng-Wei HSIEH, Yu-Pin TSAI
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Publication number: 20220181267Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes an electronic component, a conductive contact, and a first shielding layer. The electronic component has a first surface, a lateral surface angled with the first surface, and a second surface opposite to the first surface. The conductive contact is connected to the first surface of the electronic component. The first shielding layer is disposed on the lateral surface of the electronic component and a portion of the first surface of the electronic component. The first shielding layer contacts the conductive contact.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Meng-Wei HSIEH
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Patent number: 11348885Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.Type: GrantFiled: December 31, 2019Date of Patent: May 31, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin
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Publication number: 20220157709Abstract: A semiconductor package structure and method for manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a conductive pillar, a second electronic component, and a conductive through via. The conductive pillar is disposed on the first electronic component and has a first surface facing away from the first electronic component. The second electronic component is disposed on the first electronic component. The conductive through via extends through the second electronic component and has a first surface facing away from the first electronic component. The first surface of the conductive through via and the first surface of the conductive pillar are substantially coplanar.Type: ApplicationFiled: November 18, 2020Publication date: May 19, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Chiang Shih, Meng-Wei Hsieh, Hung-Yi Lin, Cheng-Yuan Kung
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Publication number: 20220148974Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.Type: ApplicationFiled: January 25, 2022Publication date: May 12, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
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Patent number: 11296043Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.Type: GrantFiled: December 4, 2019Date of Patent: April 5, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chang-Yu Lin
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Patent number: 11233010Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.Type: GrantFiled: December 31, 2019Date of Patent: January 25, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin
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Patent number: 11201125Abstract: The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.Type: GrantFiled: February 24, 2017Date of Patent: December 14, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Chi Hsieh, Hung-Yi Lin, Cheng-Yuan Kung, Pao-Nan Lee, Chien-Hua Chen
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Patent number: 11189604Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.Type: GrantFiled: October 15, 2019Date of Patent: November 30, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chao-Kai Hung, Chien-Wei Chang, Ya-Chen Shih, Hung-Jung Tu, Hung-Yi Lin, Cheng-Yuan Kung
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Publication number: 20210280744Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.Type: ApplicationFiled: March 4, 2020Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tang-Yuan CHEN, Meng-Wei HSIEH, Cheng-Yuan KUNG
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Publication number: 20210202409Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
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Publication number: 20210202392Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
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Patent number: 11037846Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.Type: GrantFiled: September 20, 2019Date of Patent: June 15, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Hsu-Chiang Shih, Cheng-Yuan Kung, Hung-Yi Lin
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Publication number: 20210175189Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.Type: ApplicationFiled: December 4, 2019Publication date: June 10, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Chang-Yu LIN
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Publication number: 20210167856Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.Type: ApplicationFiled: January 8, 2021Publication date: June 3, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Yu LIN, Cheng-Yuan KUNG, Hung-Yi LIN
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Publication number: 20210111165Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.Type: ApplicationFiled: October 15, 2019Publication date: April 15, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chao-Kai HUNG, Chien-Wei CHANG, Ya-Chen SHIH, Hung-Jung TU, Hung-Yi LIN, Cheng-Yuan KUNG