Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: A tandem solar cell and a method of manufacturing the same are provided. The tandem solar cell includes a bottom solar cell, a silicon suboxide thin film disposed over the bottom solar cell, a transparent conductive thin film disposed over the silicon suboxide thin film, and a top solar cell disposed on the transparent conductive thin film and series connected to the bottom solar cell. The silicon suboxide thin film has a refractive index of 2.0 to 3.5 for a visible light with a wavelength of 700 nm to 750 nm, and the transparent conductive thin film has a refractive index of 1.7 to 2.1 for the visible light with the wavelength of 700 nm to 750 nm. The tandem solar cell can achieve better optical matching and increase conversion efficiency.

Abstract: A method of identifying defects in crystals includes the following steps. A silicon carbide crystal to be identified for defects is sliced to obtain a test piece. An etching process is performed on the test piece. Etching conditions of the etching process includes the following. An etchant including potassium hydroxide is used, and etching is performed at a temperature of 400° C. to 550° C. in an environment where dry air or oxygen is introduced, so as to form etching pits of threading edge dislocations (TED) and threading screw dislocations (TSD) in the test piece. After the etching process is performed, a diameter ratio (TED/TSD) of the etching pits of the threading edge dislocations (TED) and the threading screw dislocations (TSD) observed by an optical microscope in the test piece is in a range of 0.2 to 0.5.

Abstract: A chemical mechanical polishing composition for polishing tungsten or molybdenum comprises, consists essentially of, or consists of a water based liquid carrier, abrasive particles dispersed in the liquid carrier, an amino acid selected from the group consisting of arginine, histidine, cysteine, lysine, and mixtures thereof, an anionic polymer or an anionic surfactant, and an optional amino acid surfactant. A method for chemical mechanical polishing a substrate including a tungsten layer or a molybdenum layer includes contacting the substrate with the above described polishing composition, moving the polishing composition relative to the substrate, and abrading the substrate to remove a portion of the tungsten layer or the molybdenum layer from the substrate and thereby polish the substrate.

Abstract: A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Abstract: An image quality evaluation system includes an image calibration device, an image capturing device, and a processing device. The image calibration device is placed in a scene and used for displaying a calibration pattern. The capturing device captures a first comparison image of the scene and the calibration pattern. The processing device is configured to obtain the first comparison image and a reference image containing the calibration pattern and compare the calibration pattern in the first comparison image and the reference image to generate calibration information. After being calibrated according to the calibration information, the image capturing device captures a second comparison image of the scene and the calibration pattern, and the processing device compares the calibration pattern in the second comparison image and the reference image to generate an image quality evaluation result.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: A semiconductor device includes a substrate having fins and trenches in between the fins, a plurality of insulators, a first metal layer, an insulating layer, a second metal layer and an interlayer dielectric. The insulators are disposed within the trenches of the substrate. The first metal layer is disposed on the plurality of insulators and across the fins. The insulating layer is disposed on the first metal layer over the plurality of insulators and across the fins. The second metal layer is disposed on the insulating layer over the plurality of insulators and across the fins. The interlayer dielectric is disposed on the insulators and covering the first metal layer, the insulating layer and the second metal layer.

Abstract: A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Abstract: A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.

Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

Abstract: A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

Abstract: A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

Abstract: A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.

Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

Abstract: A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.