Patents by Inventor Cheng-Yuan Wu

Cheng-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7242692
    Abstract: A method for coordinating packet transmission order for a plurality of registers of different priority levels is disclosed. Packets are transmitted from the registers according to the priority levels in a normal condition. A count value is generated in response to the transmitted packets. A particular priority level of one of the registers, from which a packet is being transmitted out, is recorded when the count value is larger than a predetermined threshold. Then the normal condition switches into a cleaning condition, and one packet is transmitted from each of the registers which are not empty and have priority levels lower than the particular priority level according to priority. Finally, reset the count value, and return to the normal condition. A device for coordinating packet transmission order for a plurality of registers of different priority levels is also disclosed.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: July 10, 2007
    Assignee: VIA Technologies, Inc.
    Inventors: Cheng-Yuan Wu, Stone Wei, Chih Hsien Weng
  • Patent number: 6993670
    Abstract: A method of configuring a computer system capable of being woken up on a LAN A core power is actuated for an interval by performing a Pre-Advanced Configuration and Power Interface (Pre-ACPI) routine. Next, a PCI clock signal is retrieved in the fixed interval and then an Ethernet ID is loaded using the PCI clock signal, so as to set a south bridge to a standby mode capable of receiving a wake-up event. As a result, use of an oscillator in conventional methods can be reduced, and the computer system can be configured to be capable of being woken-up on LAN, without requiring the start-up procedure, so that the computer system may be awoken on the LAN even after an abnormal shutdown.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: January 31, 2006
    Assignee: Via Technologies, Inc.
    Inventors: Chih-Hsien Weng, Wen-Hsu Huang, Cheng-Yuan Wu
  • Patent number: 6859026
    Abstract: A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p?q)th detected points but a second level at the (p+1)th detected point.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: February 22, 2005
    Assignee: Via Technologies, Inc.
    Inventors: Chen-Hua Hsi, Cheng-Yuan Wu, Chih-Hsien Weng
  • Publication number: 20040213277
    Abstract: A network interface circuit or card has a memory and a medium control module for transmitting data stored in the memory to a network. The method includes: when a packet data is transmitted (such as completely transmitted) from the memory to the medium control module, making the memory send an interrupt request such that a new packet data can be read into the memory. This results in increased data transmission efficiency in the network interface circuit.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 28, 2004
    Inventors: Cheng-Yuan Wu, Cheng-Shian Shiao
  • Publication number: 20040155642
    Abstract: A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p−q)th detected points but a second level at the (p+1)th detected point.
    Type: Application
    Filed: July 22, 2003
    Publication date: August 12, 2004
    Inventors: Chen-Hua Hsi, Cheng-Yuan Wu, Chih-Hsien Weng
  • Patent number: 6646480
    Abstract: A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: November 11, 2003
    Assignee: Via Technologies, Inc.
    Inventors: Chih Hsien Weng, Cheng-Yuan Wu, Chen-Hua Hsi
  • Publication number: 20030093589
    Abstract: A method for initializing an add-on card of a computer and a control chip capable of coupling with the add-on card is provided, wherein the chip has thereon a shadow register, the add-on card has thereon a configuration read-only memory. The method includes steps of loading basic configuration data stored in the configuration read-only memory and required for the operation of the chip to the chip, and storing the basic configuration data in the shadow register when a basic input/output system (BIOS) performs a configuration-data reading action from the configuration read-only memory, and initializing the chip in response to the basic configuration data.
    Type: Application
    Filed: August 6, 2002
    Publication date: May 15, 2003
    Inventors: Cheng-Yuan Wu, Tse Hsien Wang, Benjamin Ym Pan, Hui-Lin Chou, Chih Hsien Weng
  • Publication number: 20030086431
    Abstract: A method for coordinating packet transmission order for a plurality of registers of different priority levels is disclosed. Packets are transmitted from the registers according to the priority levels in a normal condition. A count value is generated in response to the transmitted packets. A particular priority level of one of the registers, from which a packet is being transmitted out, is recorded when the count value is larger than a predetermined threshold. Then the normal condition switches into a cleaning condition, and one packet is transmitted from each of the registers which are not empty and have priority levels lower than the particular priority level according to priority. Finally, reset the count value, and return to the normal condition. A device for coordinating packet transmission order for a plurality of registers of different priority levels is also disclosed.
    Type: Application
    Filed: July 29, 2002
    Publication date: May 8, 2003
    Applicant: Via Technologies, Inc.
    Inventors: Cheng-Yuan Wu, Stone Wei, Chih Hsien Weng
  • Publication number: 20030006808
    Abstract: A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.
    Type: Application
    Filed: May 22, 2002
    Publication date: January 9, 2003
    Applicant: VIA Technologies, Inc.
    Inventors: Chih Hsien Weng, Cheng-Yuan Wu, Chen-Hua Hsi
  • Publication number: 20020194512
    Abstract: A method of configuring a computer system capable of being woken up on LAN is disclosed. The method firstly actuates a core power for an interval by performing a Pre-Advanced Configuration and Power Interface (Pre-ACPI) routine. Next, the method retrieves a PCI clock signal in the fixed interval and then loads an Ethernet ID using the PCI clock signal, so as to set a south bridge to a standby mode capable of receiving a wake-up event. The invention can reduce an oscillator used in the conventional methods, and be capable of being woken-up on LAN without requiring the start-up procedure. And the invention can further solve the problem associated with the conventional methods, wherein an abnormal shutdown renders the computer system incapable of being woken up on LAN.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 19, 2002
    Inventors: Chih-Hsien Weng, Wen-Hsu Huang, Cheng-Yuan Wu
  • Publication number: 20010010476
    Abstract: A protecting apparatus for protecting an isolation circuit between different power domains receives a first signal, which is a level-changeable signal, from a first power domain and outputs a second signal to the isolation circuit. The apparatus includes an anti-noise circuit and a signal shaper. The anti-noise circuit receives the first signal. The signal shaper receives the output of the anti-noise circuit and outputs the second signal to the isolation circuit.
    Type: Application
    Filed: January 19, 2001
    Publication date: August 2, 2001
    Inventors: Chih-Hsien Weng, Cheng-Yuan Wu