Abstract: The disclosure discloses a heat-sealable polyester film, including a base layer and a heat-seal layer formed on the base layer. The heat-seal layer includes a physically regenerated polyester resin, a chemically regenerated polyester resin, and a modifier. The heat-sealable temperature of the heat-sealable polyester film is between 100° C. and 230° C.

Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.

Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate. The first transistor includes a first gate structure, and the second transistor includes a second gate structure. The first gate structure includes a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially formed on the substrate. The second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially formed on the substrate. The first capping layer and the second capping layer comprise materials having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.

Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.

Abstract: Implementations relate to crop yield prediction at the field- and pixel-level. In various implementations, a first temporal sequence of high-elevation digital images may be obtained that capture a first geographic area and are acquired over a first predetermined time interval while the first geographic area includes a particular crop. A first plurality of other data points may also be obtained that influence a ground truth crop yield of the first geographic area after the first predetermined time interval. The first plurality of other data points may be grouped into temporal chunks corresponding temporally with respective images of the first temporal sequence. The first temporal sequence and the temporal chunks of the first plurality of other data points may be applied, e.g., iteratively, as input across a machine learning model to estimate a crop yield of the first geographic area at the end of the first predetermined time interval.

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: A hearing aid device with functions of anti-noise and 3D sound recognition is disclosed. The hearing aid device comprises N microphones, at least one A/D converter, a modular electronic device, a D/A converter, and a loudspeaker. According to the present invention, the modular electronic device is configured for generating N second audio signals based on N first audio signals and a HRTF signal, and then summing up the N second audio signals to a reference signal. Moreover, the modular electronic device is further configured for generating a first output signal after applying an ANC process to the reference signal, converting the reference signal to a second output signal, and then generating an output signal based on the first output signal and the second output signal. Consequently, the loudspeaker broadcasts a sound according to the output signal.

Abstract: The present disclosure relates to a transformer with a modular design, the transformer comprising: a front-end assembly comprising an input electrode for receiving an input voltage; a back-end assembly comprising an output electrode, for outputting an output voltage converted by the transformer; and a magnetic core, the magnetic core being configured to assemble the front-end assembly and the back-end assembly together. The back-end assembly comprises one or more conversion modules, each conversion module being capable of independently converting the input voltage into the output voltage in collaboration with the magnetic core, and the power of the transformer is the sum of the power of all the conversion modules. The present disclosure further relates to a direct current-to-direct current converter comprising such a transformer, a vehicle comprising such a direct current-to-direct current converter, and a method for assembling such a transformer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.

Abstract: Doping a liner of a trench isolation structure with fluorine reduces dark current from a photodiode. For example, the fluorine may be added to a passivation layer surrounding a backside deep trench isolation structure. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.

Abstract: Doping a liner of a trench isolation structure with zinc and/or gallium reduces dark current from a photodiode. For example, the zinc and/or gallium may be deposited on a temporary oxide layer and driven into a high-k layer surrounding a deep trench isolation structure and an interface between the high-k layer and surrounding silicon. In another example, the zinc and/or gallium may be deposited on an oxide layer between the high-k layer and surrounding silicon. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.

Abstract: An optical imaging lens assembly includes six lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The fifth lens element has negative refractive power. The sixth lens element has positive refractive power.

Abstract: A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.

Abstract: A monitor device is provided, including: a fixing seat, for fixing to a structure; a casing, with an accommodating space, upper end of the longitudinal axis of the casing rotatably connected to the fixing seat; a first optoelectronic device, disposed on the lower end of the casing; a second photoelectric device and a third photoelectric device, respectively rotatably disposed at a first position and a second position outside the casing; a transmission mechanism, disposed in the accommodating space of the casing, and the transmission mechanism including: an angle rotation mechanism, connected to the fixing seat to drive the casing to rotate in a first direction relative to the fixing seat; and a second angle rotation mechanism connected to and driving the first, the second and the third optoelectronic device to rotate synchronously in a second direction; wherein the first direction and the second direction are orthogonal to each other.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: The present disclosure provides an electronic device. The electronic device includes a first electronic component and a second electronic component. The first electronic component is configured to receive a radio frequency (RF) signal and amplify a power of the RF signal. The second electronic component is disposed under the first electronic component. The second electronic component includes an interconnection structure passing through the second electronic component. The interconnection structure is configured to provide a path for a transmission of the RF signal.

Abstract: A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.

Abstract: This invention provides an ultrasonic transducer with a zipper array of transducing elements, which includes a tail and a head. A surface of the head is embedded with a plurality of left transducing elements and a plurality of right transducing elements, wherein each left transducing element at least partially overlaps each right transducing element in an elevation axis.

Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.