Patents by Inventor Cheng Yuan

Cheng Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTRONIC PACKAGE
    Publication number: 20230326861
    Abstract: An electronic package is provided. The electronic package includes a first processing component, a second processing component, and a first memory unit. The first memory unit is over the first processing component and the second processing component. The first processing component and the second processing component are configured to access data stored in the first memory unit.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Yi LIN, Cheng-Yuan KUNG
  • ELECTRONIC PACKAGE
    Publication number: 20230326889
    Abstract: An electronic package is provided. The electronic package includes a processing component and a memory unit. The processing component has a side including a first region and a second region distinct from the first region. The memory unit is disposed over the first region. The first region is configured to provide interconnection between the processing component and the memory unit, and the second region is configured to provide external connection.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Yi Lin, Cheng-Yuan Kung
  • Semiconductor device and method for manufacturing the same
    Patent number: 11784111
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chin-Cheng Kuo, Wu Chou Hsu
  • TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING
    Publication number: 20230317541
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • MEMORY WINDOW OF MFM MOSFET FOR SMALL CELL SIZE
    Publication number: 20230320103
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 5, 2023
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Diffusion barrier layer in programmable metallization cell
    Patent number: 11778931
    Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Zhong, Cheng-Yuan Tsai, Hai-Dang Trinh, Shing-Chyang Pan
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230298985
    Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S 11 parameter of the connector is less than ?20 dB.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Cheng Yuan CHEN, Chun Chen CHEN, Jiming LI, Chien-Wen TU
  • IMAGE SENSOR SCHEME FOR OPTICAL AND ELECTRICAL IMPROVEMENT
    Publication number: 20230299105
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Semiconductor device package, electronic assembly and method for manufacturing the same
    Patent number: 11764137
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: September 19, 2023
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Cheng Yuan Chen
  • Semiconductor package structure including shielding layer contacting conductive contact
    Patent number: 11756896
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes an electronic component, a conductive contact, and a first shielding layer. The electronic component has a first surface, a lateral surface angled with the first surface, and a second surface opposite to the first surface. The conductive contact is connected to the first surface of the electronic component. The first shielding layer is disposed on the lateral surface of the electronic component and a portion of the first surface of the electronic component. The first shielding layer contacts the conductive contact.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 12, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Meng-Wei Hsieh
  • Memory device structure with protective element
    Patent number: 11758830
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a data storage element over the semiconductor substrate. The structure also includes an ion diffusion barrier element over the data storage element and a protective element extending along a sidewall of the ion diffusion barrier element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Cheng-Yuan Tsai
  • NOTCHED WAFER AND BONDING SUPPORT STRUCTURE TO IMPROVE WAFER STACKING
    Publication number: 20230275064
    Abstract: Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 31, 2023
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • SWITCHING LAYER SCHEME TO ENHANCE RRAM PERFORMANCE
    Publication number: 20230276721
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.
    Type: Application
    Filed: May 8, 2023
    Publication date: August 31, 2023
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • SYSTEMS AND METHODS FOR AUTOMATIC JOINING AS A VIRTUAL MEETING PARTICIPANT FOR TRANSCRIPTION
    Publication number: 20230267948
    Abstract: Method, system, device, and non-transitory computer-readable medium for joining a virtual participant in a conversation. In some examples, a computer-implemented method includes: identifying a first conversation scheduled to be participated by a first group of actual participants; joining a first virtual participant into the first conversation; obtaining, via the first virtual participant, a first set of audio data associated with the first conversation while the first conversation occurs; transcribing, via the first virtual participant, the first set of audio data into a first set of text data while the first conversation occurs; and presenting the first set of text data to the first group of actual participants while the first conversation occurs.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: AMRO YOUNES, Winfred James, Tao Xing, Cheng Yuan, Yun Fu, Simon Lau, Robert Firebaugh, Sam Liang
  • Semiconductor device and fabrication method thereof
    Patent number: 11735635
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Wakeup free approach to improve the ferroelectricity of FeRAM using a stressor layer
    Patent number: 11737280
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi-Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Low-refractivity grid structure and method forming same
    Patent number: 11728364
    Abstract: A method includes forming image sensors in a semiconductor substrate, thinning the semiconductor substrate from a backside of the semiconductor substrate, forming a dielectric layer on the backside of the semiconductor substrate, and forming a polymer grid on the backside of the semiconductor substrate. The polymer grid has a first refractivity value. The method further includes forming color filters in the polymer grid, wherein the color filters has a second refractivity value higher than the first refractivity value, and forming micro-lenses on the color filters.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Cheng Yuan Wang
  • Method for manufacturing reflective structure
    Patent number: 11721794
    Abstract: A method for manufacturing reflective structure is provided. The method includes the operations as follows. A metallization structure is received. A plurality of conductive pads are formed over the metallization structure. A plurality of dielectric stacks are formed over the conductive pads, respectively, wherein the thicknesses of the dielectric stacks are different. The dielectric stacks are isolated by forming a plurality of trenches over a plurality of intervals between each two adjacent dielectric stacks.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Hua Lin, Yao-Wen Chang, Chii-Ming Wu, Cheng-Yuan Tsai, Eugene I-Chun Chen, Tzu-Chung Tsai
  • Memory window of MFM MOSFET for small cell size
    Patent number: 11723212
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • System comprising packaged optical devices
    Patent number: 11722220
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Yuan Kung, Hung-Yi Lin