Abstract: Provided are a display panel, a detection device therefor, and a display device. In an embodiment, the display panel includes an array layer, along a thickness direction of the display panel, the array layer including first and second conductive layers, and at least an insulating layer being located between the first and second conductive layers; a light-emitting element located at a side of the array layer facing a light-exiting surface of the display panel; and a first through-hole. In an embodiment, the first and second conductive layers are connected to each other through the first through-hole, and at least one first through-hole is reused as an alignment connection hole; and/or, along the thickness direction of the display panel, orthographic projections of at least two first through-holes onto a plane of the light-exiting surface of the display panel have different shapes.

Abstract: The invention provides a switching power supply and an electronic device, comprising an active clamp circuit and a transformer, the active clamp circuit including a first clamp capacitor, a second clamp capacitor, and a path guiding module that is connected at two terminals of the first clamp capacitor and two terminals of the second clamp capacitor respectively; the path guiding module, the first and the second clamp capacitors are all directly or indirectly connected to a primary side of the transformer; the path guiding module is configured to guide the first and the second clamp capacitors to obtain an electric energy from different positions on the primary side of the transformer in a first time period, and to guide the first and the second clamp capacitors to discharge the primary side of the transformer after being connected in parallel with each other in a second time period.

Abstract: The invention provides a switching power supply and an electronic device, comprising an active clamp circuit and a transformer, the active clamp circuit including a first clamp capacitor, a second clamp capacitor, and a path guiding module that is connected at two terminals of the first clamp capacitor and two terminals of the second clamp capacitor respectively; the path guiding module, the first and the second clamp capacitors are all directly or indirectly connected to a primary side of the transformer; the path guiding module is configured to guide the first and the second clamp capacitors to obtain an electric energy from different positions on the primary side of the transformer in a first time period, and to guide the first and the second clamp capacitors to discharge the primary side of the transformer after being connected in parallel with each other in a second time period.

Abstract: A power converter includes: a switching transistor, a transformer, a control circuit; the control circuit is configured to determine a target voltage in a process that the switching transistor is driven to conduct; the target voltage can represent a voltage change of an input terminal of the switching transistor; when the target voltage starts to drop but is higher than a reference voltage, drive a control terminal of the switching transistor with a first driving current; when the target voltage decreases to be lower than the reference voltage, drive the switching transistor with a second driving current; the second driving current is higher than the first driving current; the switching transistor is driven by the first driving current for part or all of the time before entering the Miller plateau stage, and is driven by the second driving current after starting to enter the Miller plateau stage.

Abstract: A power converter includes: a switching transistor, a transformer, a control circuit; the control circuit is configured to determine a target voltage in a process that the switching transistor is driven to conduct; the target voltage can represent a voltage change of an input terminal of the switching transistor; when the target voltage starts to drop but is higher than a reference voltage, drive a control terminal of the switching transistor with a first driving current; when the target voltage decreases to be lower than the reference voltage, drive the switching transistor with a second driving current; the second driving current is higher than the first driving current; the switching transistor is driven by the first driving current for part or all of the time before entering the Miller plateau stage, and is driven by the second driving current after starting to enter the Miller plateau stage.

Abstract: Provided is an anti-atopic dermatitis protein. A corresponding pharmaceutical composition contains a pharmaceutically acceptable carrier and the anti-atopic dermatitis protein. The anti-atopic dermatitis protein is one or more proteins selected from the group consisting of Helicobacter pylori-neutrophil-activating protein (HP-NAP) and recombinant maltose-binding protein fused to neutrophil-activating protein (rMBP-NAP). HP-NAP and rMBP-NAP can effectively treat AD in an oxazolone-induced AD model, providing brand-new drugs for the treatment of AD.

Abstract: An optical fiber cable with optical fiber sensing and communication functions includes an outer sheath layer, an inner sheath layer, communicating optical fibers, and sensing optical fibers. The communicating optical fibers are laid inside the inner sheath layer, the sensing optical fibers are laid between the inner sheath layer and the outer sheath layer, and an inner reinforcing member is filled in the inner sheath layer. An outer reinforcing member-is filled between the inner sheath layer and the outer sheath layer, and a plurality of cutting kerfs for slotting are provided on an outer side wall of the outer sheath layer along a length direction of the outer sheath layer. A manufacturing method includes processes of cable paying-off, molding, extruding to form sheath layers, making cutting kerfs, cooling and cable taking-up, etc., which has simple operation and low production costs.

Abstract: A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.

Abstract: An optical fiber cable with optical fiber sensing and communication functions includes an outer sheath layer, an inner sheath layer, communicating optical fibers, and sensing optical fibers. The communicating optical fibers are laid inside the inner sheath layer, the sensing optical fibers are laid between the inner sheath layer and the outer sheath layer, and an inner reinforcing member is filled in the inner sheath layer. An outer reinforcing member is filled between the inner sheath layer and the outer sheath layer, and a plurality of cutting kerfs for slotting are provided on an outer side wall of the outer sheath layer along a length direction of the outer sheath layer. A manufacturing method includes processes of cable paying-off, molding, extruding to form sheath layers, making cutting kerfs, cooling and cable taking-up, etc., which has simple operation and low production costs.

Abstract: A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the gate structures. Sidewall spacers are formed on side surfaces of the gate structures and the protective layer. A first dielectric layer is formed on the surface of the semiconductor substrate and covering the fins and the side surfaces of the sidewall spacers. A mask layer is formed on a portion of the first dielectric layer between adjacent gate structures. The mask layer and the protective layer are formed by etching a mask material layer. A second dielectric layer is formed on the first dielectric layer, the protective layer and the sidewall spacers and covering the side surfaces of the mask layer. Conductive vias are formed in the first dielectric layer between the adjacent gate structures and at both sides of the mask layer.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.

Abstract: A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.

Abstract: A switching power converter is provided that includes a current source that controls the charging of a storage capacitor to provide a regulated internal power supply voltage.

Abstract: The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.

Abstract: Systems, devices, and methods for dimming of solid state lighting reduce ripple and flicker at low load dimming levels (low LED current, lower light levels) yet provide full power to the load at high load dimming levels (high LED current, higher light levels) thereby reducing power loss compared to conventional dimming techniques. When dimming to lower light levels a flicker resisting metal oxide semiconductor field effect transistor (MOSFET) connected to the LED operates in linear mode such that the relationship of its drain-source voltage to the LED current is resistive to provide flicker reduction. Conversely, at higher light levels the flicker resisting MOSFET is operated in saturation mode such that full power is supplied to the LED as flicker reduction is less needed. The disclosed techniques also reduce undershoot and overshoot of the LED voltage during transitions in dimming control from high to low and low to high respectively.

Abstract: Various embodiments provide semiconductor devices. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.

Abstract: A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the gate structures. Sidewall spacers are formed on side surfaces of the gate structures and the protective layer. A first dielectric layer is formed on the surface of the semiconductor substrate and covering the fins and the side surfaces of the sidewall spacers. A mask layer is formed on a portion of the first dielectric layer between adjacent gate structures. The mask layer and the protective layer are formed by etching a mask material layer. A second dielectric layer is formed on the first dielectric layer, the protective layer and the sidewall spacers and covering the side surfaces of the mask layer. Conductive vias are formed in the first dielectric layer between the adjacent gate structures and at both sides of the mask layer.

Abstract: A switching power converter is provided that includes a current source that controls the charging of a storage capacitor to provide a regulated internal power supply voltage.