Abstract: A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate; forming a plurality of gate structures on the plurality of fins and sidewall spacers on side surfaces of the gate structures; forming a first dielectric layer on the semiconductor substrate; recessing the gate structures to form a plurality of trenches on top surfaces of the gate structures; forming a mask material layer filling the trenches and on the first dielectric layer; forming a protective layer on the top surfaces of the remaining gate structures and a mask layer on a portion of the first dielectric layer between adjacent gate structures by etching the mask material layer; forming contact through-holes in the first dielectric layer between adjacent gates structure at both sides of the mask layer; and forming a metal contact via in each of the contact through-holes.

Abstract: The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.

Abstract: The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer.

Abstract: An LED lamp comprises one or more LEDs, an inductive element coupled to an input voltage source and the one or more LEDs, and a switch coupled to the inductive element. A first current detector is coupled between the input voltage source and a ground node of the LED lamp, such that a current detected by the first current detector is proportional to a bulk voltage across the input voltage source. A second current detector is coupled between the inductive element and the ground node, such that current detected by the second current detector is proportional to a drain voltage across the switch. A switch controller controls the switch based on a feedback signal indicative of a voltage across the inductive element, which is generated based on a difference between the current detected by the second current detector and the current detected by the first current detector.

Abstract: A method for fabricating a semiconductor structure includes: providing a substrate with a dielectric layer and a passivation layer formed on the substrate; forming a via through the dielectric layer and exposing the substrate; forming a first conductive layer to fill the via with a top surface of the first conductive layer leveled with a top surface of the passivation layer; forming a patterned layer with an opening on the passivation layer. The opening is located above the first conductive layer with a dimension larger than the dimension of the via. The method also includes forming a trench in the dielectric layer; forming a second conductive layer to fill the trench and to electrically connect to the first conductive layer; then removing a portion of the second conductive layer, the patterned layer, and the passivation layer to make a top surface of the second conductive layer level with a top surface of the dielectric layer.

Abstract: A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines on the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein the second metal material has a different anti-electromigration ability from the first metal material.

Abstract: A method for forming an interconnect structure is provided. The method includes providing a substrate with a surface; and forming a metal layer covering the surface of the substrate and with a desired grain size to reduce grain boundary scattering of the interconnect structure subsequently formed with the metal layer. The method also includes etching the metal layer to form a plurality of metal lines on the surface of the substrate and a plurality of metal pillars on each of the plurality of the metal lines of the interconnect structure; and forming a dielectric layer covering the surface of the substrate, surfaces of the metal lines, and side surfaces of the metal pillars.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.

Abstract: An LED lamp comprises one or more LEDs and an LED driver receiving an input signal from a dimmer switch indicative of an amount of dimming for the LED lamp. The LED driver controls regulated current through the one or more LEDs based on the input signal such that an output light intensity of the one or more LEDs substantially corresponds to the amount of dimming for the LED lamp. A regulated output provides operating power for the LED driver. A controller regulates the regulated output to power the LED driver. The controller selects a power source for charging the regulated output from two or more power sources, and the regulated output is charged using the power source selected by the controller.

Abstract: An LED lamp comprises one or more LEDs, an inductive element coupled to an input voltage source and the one or more LEDs, and a switch coupled to the inductive element. A first current detector is coupled between the input voltage source and a ground node of the LED lamp, such that a current detected by the first current detector is proportional to a bulk voltage across the input voltage source. A second current detector is coupled between the inductive element and the ground node, such that current detected by the second current detector is proportional to a drain voltage across the switch. A switch controller controls the switch based on a feedback signal indicative of a voltage across the inductive element, which is generated based on a difference between the current detected by the second current detector and the current detected by the first current detector.

Abstract: A TRIAC dimmer controller for an LED lamp dynamically adjusts the amount of additional current supplied to the TRIAC dimmer based on the TRIAC dimmer operating mode. A TRIAC dimmer current controller continually senses the TRIAC dimmer current loading and determines a TRIAC dimmer operating mode based on the detected current. The TRIAC dimmer controller compares the detected current with a threshold current value called a TRIAC holding current, and adjusts the amount of bleeder current based on the difference between the detected current and the threshold current value. By continually sensing the TRIAC dimmer current loading, the LED controller regulates the amount of bleeder current supplied to the TRIAC dimmer using a single sink current path to satisfy the TRIAC dimmer current demands of multiple TRIAC dimmer operating modes.

Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.

Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.

Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.

Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.

Abstract: The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer.

Abstract: A TRIAC dimmer controller for an LED lamp dynamically adjusts the amount of additional current supplied to the TRIAC dimmer based on the TRIAC dimmer operating mode. A TRIAC dimmer current controller continually senses the TRIAC dimmer current loading and determines a TRIAC dimmer operating mode based on the detected current. The TRIAC dimmer controller compares the detected current with a threshold current value called a TRIAC holding current, and adjusts the amount of bleeder current based on the difference between the detected current and the threshold current value. By continually sensing the TRIAC dimmer current loading, the LED controller regulates the amount of bleeder current supplied to the TRIAC dimmer using a single sink current path to satisfy the TRIAC dimmer current demands of multiple TRIAC dimmer operating modes.