Patents by Inventor Chengwen Pei

Chengwen Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403772
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Juntao Li, Kangguo Cheng, Chengwen Pei, Geng Wang, Joseph Ervin
  • Patent number: 10304783
    Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Erdem Kaltalioglu, Andrew T. Kim, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 10290574
    Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Geng Wang, Kangguo Cheng, Chengwen Pei, Juntao Li
  • Patent number: 10224334
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
  • Patent number: 10224418
    Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengwen Pei, Xusheng Wu, Ziyan Xu
  • Patent number: 10199463
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Waikin Li, Chengwen Pei, Ping-Chuan Wang
  • Publication number: 20190019803
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Application
    Filed: September 4, 2018
    Publication date: January 17, 2019
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
  • Patent number: 10181468
    Abstract: An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: January 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ziyan Xu, Chengwen Pei, Xusheng Wu
  • Publication number: 20180366562
    Abstract: The disclosure is directed to methods of forming an integrated circuit structure and a related structure. One method may include: forming a gate structure over a fin, the fin being formed over a substrate and the gate structure defining a channel region beneath the gate structure within the fin; forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region; forming a rare-earth oxide (REO) within the notch and extending along a top surface of the fin outside of the notch; and forming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Xusheng Wu, Chengwen Pei, Ziyan Xu
  • Patent number: 10079280
    Abstract: After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang
  • Publication number: 20180204796
    Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 19, 2018
    Inventors: Geng Wang, Kangguo Cheng, Chengwen Pei, Juntao Li
  • Publication number: 20180190770
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Waikin LI, Chengwen PEI, Ping-Chuan WANG
  • Publication number: 20180158967
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 7, 2018
    Inventors: Juntao LI, Kangguo CHENG, Chengwen PEI, Geng WANG, Joseph ERVIN
  • Patent number: 9972621
    Abstract: A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Chengwen Pei, Ziyan Xu
  • Patent number: 9966431
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Waikin Li, Chengwen Pei, Ping-Chuan Wang
  • Publication number: 20180122795
    Abstract: An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 3, 2018
    Inventors: Ziyan Xu, Chengwen Pei, Xusheng Wu
  • Patent number: 9960226
    Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9929290
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: March 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juntao Li, Kangguo Cheng, Chengwen Pei, Geng Wang, Joseph Ervin
  • Publication number: 20180083009
    Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Roger A. BOOTH, JR., Kangguo CHENG, Joseph ERVIN, Chengwen PEI, Ravi M. TODI, Geng WANG
  • Publication number: 20180061969
    Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.
    Type: Application
    Filed: October 25, 2017
    Publication date: March 1, 2018
    Inventors: Chengwen Pei, Xusheng Wu, Ziyan Xu