Patents by Inventor Chengwen Pei
Chengwen Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9960226Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.Type: GrantFiled: July 27, 2017Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
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Patent number: 9929290Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.Type: GrantFiled: June 20, 2016Date of Patent: March 27, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Juntao Li, Kangguo Cheng, Chengwen Pei, Geng Wang, Joseph Ervin
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Publication number: 20180083009Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.Type: ApplicationFiled: November 29, 2017Publication date: March 22, 2018Inventors: Roger A. BOOTH, JR., Kangguo CHENG, Joseph ERVIN, Chengwen PEI, Ravi M. TODI, Geng WANG
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Publication number: 20180061969Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.Type: ApplicationFiled: October 25, 2017Publication date: March 1, 2018Inventors: Chengwen Pei, Xusheng Wu, Ziyan Xu
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Patent number: 9899391Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.Type: GrantFiled: January 6, 2017Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
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Patent number: 9870942Abstract: A method includes providing a semiconductor structure having a silicon mandrel layer, a hardmask stack and a dielectric layer. A 1st portion and a 2nd portion of the mandrel layer are doped with a 1st concentration and a 2nd greater concentration of dopant respectively. 1st and 2nd mandrels are patterned into the 1st and 2nd portions of the mandrel layer respectively. The 1st and 2nd mandrels are oxidized in the same thermal oxidation process to form 1st oxidation spacers on sidewalls of the 1st mandrels and 2nd oxidation spacers on sidewalls of the 2nd mandrels. The 2nd oxidation spacers have a thickness that is greater than a thickness of the 1st oxidation spacers. The 1st and 2nd oxidation spacers are utilized to form 1st and 2nd metal lines respectively in the dielectric layer. The 1st and 2nd metal lines have a different thickness.Type: GrantFiled: January 19, 2017Date of Patent: January 16, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Xusheng Wu, Ziyan Xu, Chengwen Pei
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Publication number: 20180012897Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.Type: ApplicationFiled: September 1, 2017Publication date: January 11, 2018Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
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Publication number: 20180005961Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventors: Erdem Kaltalioglu, Andrew T. Kim, Chengwen Pei, Ping-Chuan Wang
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Patent number: 9859373Abstract: After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.Type: GrantFiled: May 31, 2016Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang
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Publication number: 20170373005Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.Type: ApplicationFiled: June 22, 2016Publication date: December 28, 2017Inventors: Chengwen Pei, Kangguo Cheng, Juntao Li, Geng Wang
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Publication number: 20170373148Abstract: After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.Type: ApplicationFiled: August 24, 2017Publication date: December 28, 2017Inventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang
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Patent number: 9852982Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.Type: GrantFiled: June 22, 2016Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Chengwen Pei, Kangguo Cheng, Juntao Li, Geng Wang
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Patent number: 9852999Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.Type: GrantFiled: October 2, 2015Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: Erdem Kaltalioglu, Andrew T. Kim, Chengwen Pei, Ping-Chuan Wang
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Publication number: 20170365725Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: Juntao LI, Kangguo CHENG, Chengwen PEI, Geng WANG, Joseph ERVIN
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Publication number: 20170358691Abstract: Various particular embodiments include a semiconductor varactor structure including: a semiconductor substrate of a first conductivity type; a semiconductor area of a second conductivity type, different from the first conductivity type, within the semiconductor substrate; a field effect transistor (FET) structure within the semiconductor area; and a contact, contacting the semiconductor area, for applying a voltage bias to the semiconductor area.Type: ApplicationFiled: June 14, 2016Publication date: December 14, 2017Inventors: Kai Xiu, Chengwen Pei, Pinping Sun
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Patent number: 9842913Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.Type: GrantFiled: May 18, 2016Date of Patent: December 12, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Chengwen Pei, Xusheng Wu, Ziyan Xu
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Publication number: 20170338329Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.Type: ApplicationFiled: May 18, 2016Publication date: November 23, 2017Inventors: Chengwen Pei, Xusheng Wu, Ziyan Xu
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Patent number: 9818652Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.Type: GrantFiled: April 27, 2016Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Chengwen Pei, Ping-Chuan Wang, Kai D. Feng
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Publication number: 20170323937Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.Type: ApplicationFiled: July 27, 2017Publication date: November 9, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
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Publication number: 20170317166Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Chengwen Pei, Hanyi Ding, Ping-Chuan Wang, Kai D. Feng