Patents by Inventor Chengwen Pei

Chengwen Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170317166
    Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: Chengwen Pei, Hanyi Ding, Ping-Chuan Wang, Kai D. Feng
  • Patent number: 9806084
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
  • Publication number: 20170278927
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.
    Type: Application
    Filed: March 23, 2016
    Publication date: September 28, 2017
    Inventors: Waikin LI, Chengwen PEI, Ping-Chuan WANG
  • Patent number: 9755013
    Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9741485
    Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pinping Sun, Chengwen Pei, Zheng Xu
  • Patent number: 9735268
    Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
  • Patent number: 9691718
    Abstract: A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first shape that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9666582
    Abstract: Devices and methods are provided for constructing a semiconductor structure that implements a PUF (physical unclonable function) based on a FinFET structure. The PUF is based on a random pattern of merged and non-merged source and drain structures, which are formed on adjacent semiconductor fin structures of adjacent pairs of FinFET devices, as a result of process-induced variations in the epitaxial growth of source and drain structures on the semiconductor fin structures. The random pattern of merged and non-merged source and drain structures provides a random pattern of electrical open and short connections between pairs of semiconductor fin structures, wherein the random pattern of electrical open and short connections defines the physical unclonable function.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei
  • Publication number: 20170117280
    Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
    Type: Application
    Filed: January 6, 2017
    Publication date: April 27, 2017
    Inventors: Roger A. BOOTH, JR., Kangguo CHENG, Joseph ERVIN, Chengwen PEI, Ravi M. TODI, Geng WANG
  • Patent number: 9634084
    Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christopher D. Sheraw, Chengwen Pei, Eric T. Harley, Yue Ke, Henry K. Utomo, Yinxiao Yang, Zhibin Ren
  • Publication number: 20170098616
    Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Erdem Kaltalioglu, Andrew T. Kim, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9595518
    Abstract: Fabrication methods and structure include: providing a wafer with at least one fin extended above a substrate in a first region, and at least one fin extended above the substrate in a second region of the wafer; forming a gate structure extending at least partially over the at least one fin to define a semiconductor device region in the first region; implanting a dopant into the at least one fin in the first region and into the at least one fin in the second region of the wafer, where the implanting of the dopant into the at least one fin of the second region modulates a physical property of the at least one fin to define a resistor device region in the second region; and disposing a conductive material at least partially over the at least one fin in the first region and over the at least one fin in the second region of the wafer, in part, to form a source and drain contact in the first region, and a fin-type metal-semiconductor resistor in the second region.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony I-Chih Chou, Chengwen Pei, Edward P. Maciejewski, Ning Zhan
  • Patent number: 9583497
    Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 9576914
    Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9557290
    Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang
  • Patent number: 9559202
    Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
  • Patent number: 9530701
    Abstract: An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel. The approach includes depositing a layer of a dielectric material on the semiconductor layer and around the mandrel and etching the layer of the dielectric material to form one or more spacers next to the sidewalls of the mandrel, followed by removing the mandrel. Additionally, the approach includes depositing a layer of amorphous semiconductor material around said one or more spacers and heating it to transform into a layer of re-crystallized semiconductor material through solid phase epitaxy. Furthermore, the approach includes removing portions of the layer of re-crystallized semiconductor material from each of the horizontal surfaces of the silicon-on-insulator wafer including the area where the one or more spacers were removed to form one or more fins.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang
  • Publication number: 20160343664
    Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
  • Publication number: 20160329287
    Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 10, 2016
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9490223
    Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang