Patents by Inventor Cheol Soo Park

Cheol Soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6919246
    Abstract: A semiconductor device and method for fabricating the same. The semiconductor device comprises a capacitor including a semiconductor substrate having a first conductive type well; a first trench formed in the semiconductor substrate; a plate electrode formed on the first trench; a capacitor insulating film formed on the plate electrode; and a storage node electrode formed in the first trench. The transistor includes a first insulating film for planarization formed on the storage node electrode; a second trench formed in the portion of the first conductive type well, which does not correspond to the first trench; a gate insulating film formed on the second trench; a gate electrode formed on the portion of the gate insulating film, located on the second trench; and drain and source regions formed on the upper and lower portions of the first conductive type well, respectively, which corresponds to the sidewall of the second trench.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 19, 2005
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: Cheol Soo Park
  • Patent number: 6870214
    Abstract: A flash EEPROM cell and fabricating method thereof. The cell comprises: a silicon substrate; a silicon pillar layer formed on the silicon substrate; a tunnel insulating film and a floating electrode, formed on the silicon pillar layer; a control gate insulating film and a control gate electrode, formed on the floating electrode; a source region formed in the silicon substrate; a drain region formed on the silicon pillar layer; and bit lines formed on the drain region. The method comprises: providing a silicon substrate; forming a silicon pillar layer on the silicon substrate; forming a tunneling insulating film and a floating electrode; successively forming a control gate insulating film and a control gate electrode; forming a source region and a drain region in the silicon substrate, and on the silicon pillar layer, respectively; and forming bit lines.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: March 22, 2005
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6867095
    Abstract: A method for fabricating a semiconductor device comprising: providing a semiconductor substrate on which a transistor made of a gate electrode, a source/drain is formed; forming a first insulating layer on the semiconductor substrate, with bit-line contact holes and a storage node contact hole being formed in the insulating layer to expose the source and drain; forming bit-line contact plugs and storage node in the bit-line contact holes and the storage node contact hole; removing the first insulating layer; forming a second insulating layer on the resultant structure; forming a first conductive layer on the second insulating layer; forming a third insulating layer; forming bit-line contact holes by selective removal of the first conductive layer and the third insulating layer opposing the upper surface of the bit-line contact plug; and forming a second conductive layer in the bit-line contact holes.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: March 15, 2005
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6849551
    Abstract: Disclosed is a method for forming an isolation region in a semiconductor device. Pad oxide and nitride films are sequentially formed on a silicon substrate. Photoresist pattern is formed on the pad nitride film, the photoresist pattern. Respectively predetermined parts of the pad oxide and nitride films and the silicon substrate are etched by using the photoresist pattern as a mask to form a shallow trench. Field implant process is performed on a lower surface of the shallow trench, by using the photoresist pattern as a mask to form a field stop implant film. Photoresist pattern is removed. The inside of the shallow trench is washed. The inside of the shallow trench is thermally enlarged to form a first oxide film. Second oxide film is deposited on the first oxide film and chemical mechanical polishing process for the second oxide film is performed to form the isolation region.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: February 1, 2005
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6849552
    Abstract: A vertical type transistor and fabricating method therefor. An isolation oxide layer is formed on a field region in a silicon substrate to expose an active region, and an epitaxial silicon layer is formed on the active region of a source region is formed in the vicinity of the surface of the silicon substrate and a drain region is formed on the epitaxial silicon layer. A masking insulator spacer is formed at the side wall of stair part, and the epitaxial silicon layer exposed through the masking insulator spacer is removed. A gate insulating layer is formed along with the exposed surfaces of the epitaxial silicon layer, the source region, and the drain region. A gate electrode is formed to contact with the gate insulating layer. A planarization insulating layer is formed over whole structure, and contact holes and contact plugs are formed thereon.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: February 1, 2005
    Assignee: Dongbu Electronics Co., Ltd
    Inventor: Cheol Soo Park
  • Patent number: 6833232
    Abstract: Disclosed is a micro-pattern forming method for a semiconductor device comprising: sequentially forming first and second insulation films on a semiconductor substrate; forming a photosensitive film on the second insulation film; dry etching the second insulation film; removing the photosensitive film; forming a third insulation film on the substrate; forming a fourth insulation film on a resultant structure; etching the third and fourth insulation films using a proper formal solution; etching the third insulation film using the fourth and second insulation films as masks to form a third insulation film pattern; and filling a conductive film into spaces between the second and third insulation films and second flattening the conductive film to form conductive lines.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: December 21, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6765263
    Abstract: The present invention relates to a semiconductor device and a fabricating method thereof. The fabricating method comprises: forming an insulating film on a silicon substrate; forming a first conductive well of a first conductive type in the silicon substrate; first and second conductive layers of a second conductive type at a portion below the surface of the first conductive well and in the inner region of the first conductive well, respectively; patterning the insulating film and the first conductive layer of the second conductive type, so that contact holes are formed in such a manner that the second conductive layer formed in the inner region of the first conductive well is exposed through the contact holes; forming a gate insulating film on the sidewall of the first conductive well in the contact holes; and forming a gate electrode on the surface of the gate insulating film in the contact holes.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: July 20, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6743665
    Abstract: Disclosed is a method for forming an isolation layer in a semiconductor device, in which when a masking insulation layer and an isolation oxide layer are sequentially subjected to a dry etching process in accordance with an isolation mask pattern, the isolation oxide layer is etched to have a thickness of approximately hundreds of angstroms from the top surface of the silicon substrate, thereby preventing the silicon substrate from being damaged by plasma. Therefore, reliability of the device can be improved. To this end, the method comprises the steps of forming an isolation oxide layer and a masking insulation layer on an silicon substrate in order; etching the masking insulation layer and the isolation oxide to form a trench; and growing an epitaxial silicon layer in the trench to form an epitaxial silicon active area.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: June 1, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6734058
    Abstract: A method for fabricating a semiconductor device comprising forming an insulating layer and a nitride layer sequentially on a semiconductor substrate; selectively removing the layers to form a first contact hole; forming a silicon layer in the first contact hole; forming a trench by selective removal of the silicon layer; forming a source region in the semiconductor substrate and a drain region on the trench; forming a gate oxide layer and gates sequentially at the side walls of the trench; forming a planarization layer on the resultant structure; forming a second contact hole that exposes the gate, the drain region, and the source region; and forming plugs in the exposed second contact hole.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: May 11, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6689664
    Abstract: A transistor fabrication method comprises: sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate; etching the substrate to form a trench; sequentially forming a first oxide film within the trench and a cylindrical insulation spacer at a lateral portion of the first oxide film; forming an insulation pattern; etching the silicon nitride film, the insulation pattern and the insulation spacer; removing the pad oxide film; removing the insulation spacer and the first oxide film; sequentially forming source/drain regions and LDD regions at both sides of the trench, under the remaining insulation pattern; forming a second oxide film; sequentially forming a channel stop layer between the LDD regions and a punch stop layer under the channel stop layer; and sequentially forming a gate insulation film and a gate region within the trench and the second oxide layer.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: February 10, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6674910
    Abstract: An apparatus and method for image-compression encoding and decoding using an adaptive transform in which, where different transform coefficients are outputted in accordance with a change of the transform direction order for an input image signal block, encoding and decoding procedures are conducted, based on the transform direction order selected in accordance with the characteristics of the input image signal block. In accordance with the present invention, an orthogonal transform and a inverse orthogonal transform for blocks are controlled, based on a determination made about whether signals within a block, to be currently encoded, have a higher correlation in a vertical direction or in a horizontal direction, using information about blocks encoded or both information about blocks encoded and information about the current block.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: January 6, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Joo Hee Moon, Cheol Soo Park, Joon Ho Song
  • Patent number: 6642130
    Abstract: A method for fabricating a transistor comprises steps of forming a conductive well region, an isolation oxide layer, a first pad oxide layer, a conductive LDD (low doped drain) region and a source/drain region on a silicon substrate. A pad nitride layer is formed on the first oxide layer. A trench is fanned by etching the pad nitride layer, the first oxide layer, the source/drain region, and the LDD region. A second pad oxide layer is then formed on the source/drain region and LDD region. The LDD region and part of the well region are removed after removal of the second pad oxide layer. A gate is formed in the trench, and an interlayer insulating layer is formed on the resultant structure.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: November 4, 2003
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Publication number: 20030180669
    Abstract: Disclosed is a micro-pattern forming method for a semiconductor device comprising: sequentially forming first and second insulation films on a semiconductor substrate; forming a photosensitive film on the second insulation film; dry etching the second insulation film; removing the photosensitive film; forming a third insulation film on the substrate; forming a fourth insulation film on a resultant structure; etching the third and fourth insulation films using a proper formal solution; etching the third insulation film using the fourth and second insulation films as masks to form a third insulation film pattern; and filling a conductive film into spaces between the second and third insulation films and second flattening the conductive film to form conductive lines.
    Type: Application
    Filed: January 8, 2003
    Publication date: September 25, 2003
    Inventor: Cheol Soo Park
  • Patent number: 6599825
    Abstract: A method for forming wiring in a semiconductor device comprises the steps of: forming a trench in a desired place on a silicon substrate, forming a thermal oxidation layer on the surface of the trench, forming wiring by filling a conductive layer in the lower part of the trench, forming an insulating layer on the wiring, removing the thermal oxidation layer over the insulating layer, forming an epitaxial silicon layer so that the trench is filled completely, forming a contact hole exposing the wiring by etching the epitaxial silicon layer and the insulating layer, forming an insulating spacer on the side walls of the contact hole, and forming a wiring plug in the contact hole in which the insulating layer has been formed. In the method for forming such wiring in the semiconductor device, metal wiring is formed in the silicon substrate.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: July 29, 2003
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheol Soo Park
  • Patent number: 6597738
    Abstract: A motion descriptor generating apparatus using accumulated motion histogram and a method therefor. Accumulated motion histograms are generated and motion descriptors are generated by using the accumulated motion histograms. The motion descriptor generating apparatus uses an accumulated motion histogram and includes a motion histogram generating unit for respectively generating a motion histogram with relation to intensity data and direction data of an input motion. An accumulated motion histogram generating unit generates a two-dimensional accumulated motion histogram in a predetermined sequence by using the motion histogram which is generated in the motion histogram generating unit. A motion descriptor generating unit structures (hierarchy structure) video into certain units according to a change amount of the accumulated motion histogram based on a lapse of time, which is generated in the accumulated motion intensity histogram generating unit.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: July 22, 2003
    Assignee: Hyundai Curitel, Inc.
    Inventors: Cheol-Soo Park, Hae-Kwang Kim, Joo-Hee Moon
  • Publication number: 20030122184
    Abstract: A flash EEPROM cell and fabricating method thereof. The cell comprises: a silicon substrate; a silicon pillar layer formed on the silicon substrate; a tunnel insulating film and a floating electrode, formed on the silicon pillar layer; a control gate insulating film and a control gate electrode, formed on the floating electrode; a source region formed in the silicon substrate; a drain region formed on the silicon pillar layer; and bit lines formed on the drain region. The method comprises: providing a silicon substrate; forming a silicon pillar layer on the silicon substrate; forming a tunneling insulating film and a floating electrode; successively forming a control gate insulating film and a control gate electrode; forming a source region and a drain region in the silicon substrate, and on the silicon pillar layer, respectively; and forming bit lines.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 3, 2003
    Inventor: Cheol Soo Park
  • Publication number: 20030119252
    Abstract: A method for fabricating a semiconductor device comprising: providing a semiconductor substrate on which a transistor made of a gate electrode, a source/drain is formed; forming a first insulating layer on the semiconductor substrate, with bit-line contact holes and a storage node contact hole being formed in the insulating layer to expose the source and drain; forming bit-line contact plugs and storage node in the bit-line contact holes and the storage node contact hole; removing the first insulating layer; forming a second insulating layer on the resultant structure; forming a first conductive layer on the second insulating layer; forming a third insulating layer; forming bit-line contact holes by selective removal of the first conductive layer and the third insulating layer opposing the upper surface of the bit-line contact plug; and forming a second conductive layer in the bit-line contact holes.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 26, 2003
    Inventor: Cheol Soo Park
  • Publication number: 20030119264
    Abstract: A method for fabricating a highly integrated transistor comprises the steps of forming a first conductive well region on a silicon substrate, forming an isolation oxide layer on the desired region of the entire surface of the silicon substrate, forming a first pad oxide layer on the entire surface of the silicon substrate, forming a second conductive LDD (low doped drain) region and a second source/drain region on an active region of the silicon substrate, and forming a pad nitride layer on the first oxide layer.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 26, 2003
    Inventor: Cheol Soo Park
  • Publication number: 20030119323
    Abstract: A method for fabricating a transistor in a semiconductor device can minimize short-channel effects (SCE), reverse short-channel effects (RSCE), gate induced drain leakage (GIDL), and off leakage of a transistor and can reduce production costs through fabricating the transistor through a simple process.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 26, 2003
    Inventor: Cheol Soo Park
  • Publication number: 20030116803
    Abstract: A cylinder type transistor and a fabrication method thereof. The transistor comprises: a well zone of a first conductive type formed on a silicon substrate; a drain of a second conductive type formed at a predetermined depth of the well zone; a plurality of silicon bulks located in the well zone above the drain; a source of the second conductive type formed on the silicon bulks; a gate filling the inside of the silicon bulks with a gate oxide layer interposed therein; an isolation oxide layer formed on an entire surface of a resultant structure, exposing a portion of the gate, the source and the drain; and contact plugs one electrically connected to the gate, the source and the drain, respectively, as exposed through the isolation oxide layer.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 26, 2003
    Inventor: Cheol Soo Park