Cheol Soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A vertical type transistor and fabricating method therefor. An isolation oxide layer is formed on a field region in a silicon substrate to expose an active region, and an epitaxial silicon layer is formed on the active region of a source region is formed in the vicinity of the surface of the silicon substrate and a drain region is formed on the epitaxial silicon layer. A masking insulator spacer is formed at the side wall of stair part, and the epitaxial silicon layer exposed through the masking insulator spacer is removed. A gate insulating layer is formed along with the exposed surfaces of the epitaxial silicon layer, the source region, and the drain region. A gate electrode is formed to contact with the gate insulating layer. A planarization insulating layer is formed over whole structure, and contact holes and contact plugs are formed thereon.
Abstract: A method for forming wiring in a semiconductor device comprises the steps of: forming a trench in a desired place on a silicon substrate, forming a thermal oxidation layer on the surface of the trench, forming wiring by filling a conductive layer in the lower part of the trench, forming an insulating layer on the wiring, removing the thermal oxidation layer over the insulating layer, forming an epitaxial silicon layer so that the trench is filled completely, forming a contact hole exposing the wiring by etching the epitaxial silicon layer and the insulating layer, forming an insulating spacer on the side walls of the contact hole, and forming a wiring plug in the contact hole in which the insulating layer has been formed. In the method for forming such wiring in the semiconductor device, metal wiring is formed in the silicon substrate.
Abstract: A semiconductor device and a method for fabricating the same. The device comprises a silicon substrate having a conductive well; a trench formed in the conductive well; a plate electrode formed on the sidewall of the trench; a capacitor insulating film and a storage node electrode; a first storage node connector formed on the storage node electrode; an insulating film formed on the first storage node connector; a silicon layer formed on the entire structure; word lines formed on the silicon layer; source and drain regions formed in the silicon layer; a contact hole, formed in the silicon layer and the insulating film, such that the first storage node connector and the source region are exposed; and a second storage node connector, formed in the contact hole, such that the source region and the first storage node connector are connected to each other.
Abstract: A transistor fabrication method comprises: sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate; etching the substrate to form a trench; sequentially forming a first oxide film within the trench and a cylindrical insulation spacer at a lateral portion of the first oxide film; forming an insulation pattern; etching the silicon nitride film, the insulation pattern and the insulation spacer; removing the pad oxide film; removing the insulation spacer and the first oxide film; sequentially forming source/drain regions and LDD regions at both sides of the trench, under the remaining insulation pattern; forming a second oxide film; sequentially forming a channel stop layer between the LDD regions and a punch stop layer under the channel stop layer; and sequentially forming a gate insulation film and a gate region within the trench and the second oxide layer.
Abstract: The present invention relates to a semiconductor device and a fabricating method thereof. The fabricating method comprises: forming an insulating film on a silicon substrate; forming a first conductive well of a first conductive type in the silicon substrate; first and second conductive layers of a second conductive type at a portion below the surface of the first conductive well and in the inner region of the first conductive well, respectively; patterning the insulating film and the first conductive layer of the second conductive type, so that contact holes are formed in such a manner that the second conductive layer formed in the inner region of the first conductive well is exposed through the contact holes; forming a gate insulating film on the sidewall of the first conductive well in the contact holes; and forming a gate electrode on the surface of the gate insulating film in the contact holes.
Abstract: Disclosed is a method for forming an isolation region in a semiconductor device. Pad oxide and nitride films are sequentially formed on a silicon substrate. Photoresist pattern is formed on the pad nitride film, the photoresist pattern. Respectively predetermined parts of the pad oxide and nitride films and the silicon substrate are etched by using the photoresist pattern as a mask to form a shallow trench. Field implant process is performed on a lower surface of the shallow trench, by using the photoresist pattern as a mask to form a field stop implant film. Photoresist pattern is removed. The inside of the shallow trench is washed. The inside of the shallow trench is thermally enlarged to form a first oxide film. Second oxide film is deposited on the first oxide film and chemical mechanical polishing process for the second oxide film is performed to form the isolation region.
Abstract: A semiconductor device and method for fabricating the same. The semiconductor device comprises a capacitor including a semiconductor substrate having a first conductive type well; a first trench formed in the semiconductor substrate; a plate electrode formed on the first trench; a capacitor insulating film formed on the plate electrode; and a storage node electrode formed in the first trench. The transistor includes a first insulating film for planarization formed on the storage node electrode; a second trench formed in the portion of the first conductive type well, which does not correspond to the first trench; a gate insulating film formed on the second trench; a gate electrode formed on the portion of the gate insulating film, located on the second trench; and drain and source regions formed on the upper and lower portions of the first conductive type well, respectively, which corresponds to the sidewall of the second trench.
Abstract: Disclosed is a method for forming an isolation layer in a semiconductor device, in which when a masking insulation layer and an isolation oxide layer are sequentially subjected to a dry etching process in accordance with an isolation mask pattern, the isolation oxide layer is etched to have a thickness of approximately hundreds of angstroms from the top surface of the silicon substrate, thereby preventing the silicon substrate from being damaged by plasma. Therefore, reliability of the device can be improved. To this end, the method comprises the steps of forming an isolation oxide layer and a masking insulation layer on an silicon substrate in order; etching the masking insulation layer and the isolation oxide to form a trench; and growing an epitaxial silicon layer in the trench to form an epitaxial silicon active area.
Abstract: An image chrominance signal filtering method and apparatus in which object chrominance information and background chrominance information are extracted in an image format conversion process, based on shape information of luminance signals, and then decimation-filtered or interpolation-filtered. In accordance with the method and apparatus of the present invention, it is possible to avoid a color bleeding phenomenon occurring at the boundaries of objects in an image. Accordingly, there is an advantage in that a degradation in picture quality is prevented.
June 18, 1999
Date of Patent:
June 10, 2003
Hyundai Electronics Ind. Co., LTD
Cheol Soo Park, Joo Hee Moon, Hae Kwang Kim
Abstract: A method and system for contour-based motion estimation for use with video images. The invention establishes corresponding contours (404, 414) in two images (402, 412) in a sequence of images, determines a motion vector which includes how the first contour (404) moved to become the second contour (414), and transmits the motion vector of the contour (414) in order to permit accurate display of the second video image (412). Preferably, boundary lines are removed from the contours before a comparison is made. The invention is computationally efficient and economical from a data transmission point of view, while enabling the production of accurate image.
November 17, 1998
Date of Patent:
July 16, 2002
Hyundai Curitel, Inc.
Jae-Won Chung, Cheol-Soo Park, Joo-Hee Moon, Jae-Kyoon Kim
Abstract: A method and apparatus for generating a bounding rectangle of a VOP for interlaced scan type video signals, which are capable of accurately generating a bounding rectangle, thereby preventing a color bleeding from occurring in the field-based chrominance shape subsampling. The method includes bounding rectangle formation step of forming a bounding rectangle of a video object plane in such a fashion that the bounding rectangle contains an object therein, based on input luminance shape information, optimum setting determination step of determining whether or not a spatial reference point of the bounding rectangle is positioned on an x-y coordinate of coordinate value (2m, 4n) (m and n=0, 1, 2, 3, 4, . . .
Abstract: The present invention relates to a method of forming a contact of a semiconductor device, and more particularly, to a method of forming a contact of a semiconductor device that can improve the process yield of the device and reliability by simplifying the process of forming the contact hole of the top conductive layer without removing the etching barrier layer of the portion on which the contact hole of the top conductive layer is to be formed when a storage electrode contact is formed, where the contact hole of the top conductive layer is formed on the top of the bottom conductive layer, which refers to a process of forming the self-alignment contact.
Abstract: A method for forming a capacitor of a semiconductor device, by which a three dimensional structure of a storage electrode occupying small space but having a great surface area is formed between word lines or bit lines. According to the method, an additional planarization layer is not formed on the word lines or the bit lines, so as to make the three dimensional structure high. Thus, the storage electrode comes to have an enlarged surface area enough to allow the formation of a capacitor with a sufficient capacitance for the high integration of semiconductor devices and thus to improve the properties and the reliability of semiconductor devices.
Abstract: A DRAM capacitor and a method for fabricating the same, capable of achieving an increase in surface area and thereby an increase in capacitance while reducing the topology, by simply forming a conduction layer, as a charge storage electrode, comprised of conduction spacers around a double-layer pin-shaped conduction layer pattern or a combination of a central conduction layer pattern and an outer conduction layer pattern having an upwardly-opened dome structure surrounding the central conduction layer pattern, using an etch rate difference between insulating films.
Abstract: When contacting a bit line and a charge storage electrode to a source/drain of the MOS transistor during a manufacturing process of a highly integrated semiconductor device, a contact pad is formed by filling up polysilicon into a contact hole that had been made using a self-align method in order not to damage the word line or the bit line as a result of a small processing margin during a contact hole forming process. Also, the occurrence of a topological difference during a semiconductor manufacturing process is minimized by forming an oxide layer such as SOG, BPSG, TEOS, and PECVD oxide over the top of the field oxide for a flattening effect.