Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

Abstract: A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.

Abstract: A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar.

Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.

Abstract: A resistive random access memory (ReRAM) device can comprise a first metal layer and a first metal-oxide layer on the first metal layer. The first metal-oxide layer comprises the first metal. A second metal layer can comprise a second metal over and in physical contact with the first metal-oxide layer. A first continuous non-conductive barrier layer can be in physical contact with sidewalls of the first metal layer and sidewalls of the first metal-oxide layer. A second metal-oxide layer can be on the second metal layer. The second metal-oxide layer can comprise the second metal layer. A third metal layer can be over and in physical contact with the second metal-oxide layer. The first and second metal-oxide layers, are further characterized as independent storage mediums.

Abstract: A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

Abstract: A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.

Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

Abstract: A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each DGO transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.

Abstract: A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region.

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having patterned select gates (211, 213), charge storage layers (219), inlaid control gates (223, 224), and inlaid control gate contact regions (228).

Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar dielectric layers (116) prior to forming an elevated substrate (117) on a second CMOS transistor area (112) on which high-k metal gate electrodes (119-120, 122-126, 132, 134) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

Abstract: A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent to the performing the first programming of the split gate memory cell, performing a second programming of the split gate memory cell in the first programming cycle, wherein the first programming is characterized as one of source-side injection (SSI) programming and channel-initiated secondary electron (CHISEL) programming, and the second programming is characterized as the other of SSI programming and CHISEL programming.

Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

Abstract: A method includes forming a first conductive layer over a substrate in a first region and second region of the substrate; patterning the first conductive layer to form a select gate in the first region and to remove the first conductive layer from the second region; forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region; forming a second conductive layer over the charge storage layer in the first and second regions; and patterning the second conductive layer and charge storage layer to form a control gate overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and control gate, and to form an electrode in the second region, wherein a second portion of the charge storage layer remains between the electrode and substrate.