Patents by Inventor Cheong Min Hong

Cheong Min Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120261636
    Abstract: A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Inventors: Feng Zhou, Ko-Min Chang, Cheong Min Hong
  • Publication number: 20120261635
    Abstract: A resistive random access memory cell over a substrate includes a memory stack structure and a sidewall spacer. The memory stack structure is over the substrate and includes a first electrode layer, a second electrode layer, and a metal oxide layer between the first electrode layer and the second electrode layer. The metal oxide layer has a sidewall. The sidewall spacer is adjacent to the sidewall and has a composition including silicon, carbon, and nitrogen.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Inventors: Feng Zhou, Ko-Min Chang, Cheong Min Hong
  • Patent number: 8193572
    Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: June 5, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chi-Nan Li, Cheong Min Hong
  • Patent number: 8163609
    Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: April 24, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 8048738
    Abstract: A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: November 1, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sung-Taeg Kang, Cheong Min Hong, Brian A. Winstead
  • Publication number: 20110256705
    Abstract: A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 20, 2011
    Inventors: Sung-Taeg Kang, Cheong Min Hong, Brian A. Winstead
  • Publication number: 20110073936
    Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.
    Type: Application
    Filed: December 9, 2010
    Publication date: March 31, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 7871886
    Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: January 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 7838922
    Abstract: An electronic device can include a substrate including a trench having a bottom and a first wall. The electronic device can also include a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, a second gate electrode overlying the substrate outside of the trench, and a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench. The electronic device can also include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench. Processes of forming and using the electronic device are also described.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chi-Nan Li, Cheong Min Hong
  • Publication number: 20100155824
    Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.
    Type: Application
    Filed: May 6, 2009
    Publication date: June 24, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Publication number: 20100096686
    Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.
    Type: Application
    Filed: December 24, 2009
    Publication date: April 22, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Chi-Nan Li, Cheong Min Hong
  • Patent number: 7651916
    Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: January 26, 2010
    Assignee: Freescale Semiconductor, Inc
    Inventors: Chi-Nan Li, Cheong Min Hong
  • Patent number: 7572699
    Abstract: An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and a second gate electrode within the second trench and adjacent to the fin. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin. Processes of forming and using the electronic device are also described.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: August 11, 2009
    Assignee: Freescale Semiconductor, Inc
    Inventors: Cheong Min Hong, Chi-Nan Li
  • Publication number: 20080173921
    Abstract: An electronic device can include a substrate including a trench having a bottom and a first wall. The electronic device can also include a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, a second gate electrode overlying the substrate outside of the trench, and a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench. The electronic device can also include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench. Processes of forming and using the electronic device are also described.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chi-Nan Li, Cheong Min Hong
  • Publication number: 20080173923
    Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chi-Nan Li, Cheong Min HONG
  • Publication number: 20080173922
    Abstract: An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and a second gate electrode within the second trench and adjacent to the fin. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin. Processes of forming and using the electronic device are also described.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Cheong Min HONG, Chi-Nan LI