Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.

Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The second supply metal tract is wider than the first supply metal tract. The first supply metal tract has a thickness substantially same as the first pattern metal layer. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.

Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.

Abstract: Some embodiments relate to a sense amplifier. The sense amplifier includes a fully-depleted silicon on insulator (FDSOI) substrate, including a handle substrate region, an insulator layer over the handle substrate region, and a device region over the insulator layer. An n-well region is disposed in the handle substrate region, and an n-well contact region extends from the n-well region through the insulator layer to an upper surface of the device region. A pair of pull-down transistors are disposed in the device region and over the n-well. The pair of pull-down transistors have their respective gates coupled to a pair of complementary bitlines, respectively, and coupled to the n-well through the n-well contact region.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

Abstract: A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.

Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.

Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.

Abstract: An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

Abstract: The present disclosure relates to an integrated circuit having a via rail that prevents reliability concerns such as electro-migration. In some embodiments, the integrated circuit has a first plurality of conductive contacts arranged over a semiconductor substrate. A first metal interconnect wire is arranged over the first plurality of conductive contacts, and a second metal interconnect wire is arranged over the first metal interconnect wire. A via rail is arranged over the first metal interconnect wire and electrically couples the first metal interconnect wire and the second metal interconnect wire. The via rail has a length that continuously extends over two or more of the plurality of conductive contacts. The length of via rail provides for an increased cross-sectional area both between the first metal interconnect wire and the second metal interconnect wire and along a length of the via rail, thereby mitigating electro-migration within the integrated circuit.