Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.

Abstract: The present invention relates to a method for making chip assemblies, including the following steps of: (a) providing a tested upper wafer and at least one tested lower wafer; (b) sawing the at least one tested lower wafer to form a plurality of lower dice, the lower dice including a plurality of know good lower dice; (c) picking up and rearranging the know good lower dice on a carrier according to the wafer map of the upper wafer; (d) bonding the upper wafer and the carrier; (e) removing the carrier; and (f) proceeding sawing step. Whereby, the dice of the die assembly are both known good dice, thus the yield loss caused by the different yields between the upper wafer and the lower wafer will not occur.

Abstract: A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.

Abstract: In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.

Abstract: A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.

Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the side walls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the side walls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

Abstract: A package process is provided. First, a semiconductor substrate is disposed on a carrier, in which a surface of the carrier has an adhesive layer and the semiconductor substrate is bonded to the carrier by the adhesive layer. Next, a chip is bonded on the semiconductor substrate by flip chip technique and a first underfill is formed between the chip and the semiconductor substrate to encapsulate a plurality of first conductive bumps at the bottom of the chip. Then, a first molding compound is formed on the semiconductor substrate. The first molding compound at least encapsulates the side surface of the chip and the first underfill. Finally, the semiconductor substrate together with the chip and the first molding compound located thereon are separated from the adhesive layer of the carrier to form an array package structure.

Abstract: A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.

Abstract: A chip scale package (CSP) package and method of fabricating the same are provided. The fabricating method includes the following steps. First, a substrate is provided. Next, a chip is disposed on the front surface of the substrate and electrically connected to the substrate. Then, a thermal conductive paste is formed on the surface of the chip. Afterwards, a molding compound for enclosing the chip is formed. Lastly, a milling process is applied to the molding compound so that the height of the molding compound is aligned with that of the thermal conductive paste. The chip can be disposed on the substrate by way of wire bonding or flip-chip bonding. The thermal conductive paste is disposed on the surface of the chip either before or after the milling process is completed.

Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.

Abstract: In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.

Abstract: A circuit substrate suitable for being connected to at least one solder ball is provided. The circuit substrate includes a substrate, at least one bonding pad, and a solder mask. The substrate has a surface. The bonding pad is disposed on the surface of the substrate for being connected to the solder ball. The solder mask covers the surface of the substrate and has an opening for exposing a portion of the bonding pad. The opening has a first end and a second end. As compared with the second end, the first end is much farther from the bonding pad, and a diameter of the first end is larger than that of the second end.

Abstract: A chip package structure and process are provided; the structure includes a substrate, a chip, a solder layer and at least a stud bump. The substrate has at least a contact pad, and the chip has an active surface where at least a bonding pad is disposed. The stud bump is disposed on the bonding pad of the chip or on the contact pad of the substrate, and the stud bump joints with the solder layer to fix the chip on the substrate. The stud bump is made of gold-silver alloy containing silver below 15% by weight.

Abstract: A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.

Abstract: A stacked type chip package structure including a package structure, a corresponding substrate, and a number of second bumps is provided. The package structure includes a first chip, a second chip, a number of first bumps, and a first underfill. The first chip is disposed above the second chip. The first bumps are disposed between the first chip and the second chip for electrically connecting the first chip and the second chip. The first underfill is used to fill between the first chip and the second chip and encapsulates the first bumps. The package structure is disposed above the corresponding substrate in a reverse manner, such that the first chip is disposed between the second chip and the corresponding substrate. The second bumps are disposed between the second chip and the corresponding substrate, such that the second chip is electrically connected to the corresponding substrate through the second bumps.

Abstract: A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks.

Abstract: A mold for an integrated circuit package. The mold for an integrated circuit package includes a main cavity, a front cavity, a rear cavity, a plurality of gates and a plurality of air vents. The gates and the air vents are located on two opposite sides of the mold respectively. The front cavity is located between the main cavity and the gates and the rear cavity is located between the main cavity and the air vents. The gates, the front cavity, the main cavity, the rear cavity and the air vents are interconnected so that they share a common inner space. The extension direction of the rear cavity is parallel to the arrangement direction of the air vents, and the extension direction of the front cavity is parallel to the arrangement direction of the gates. The width of the rear cavity is much smaller than the width of the main cavity.

Abstract: A method and apparatus for molding a flip chip semiconductor device are disclosed herein. A substrate having at least one air hole is provided. A chip is mounted on the substrate by multiple solder balls such that the air hole is beneath the chip and surrounded by the multiple solder balls. The substrate mounted with the chip is placed in a mold apparatus which defines at least one air channel aligning with the air hole, such that air can be exhausted via the air hole and the air channel when encapsulation material is filling the mold apparatus.