Abstract: A thermal management system for an electronic device, including: a primary thermal conductivity spreader; a first heat-generating component thermally coupled to the primary thermal conductivity spreader; and a secondary thermal conductivity spreader layer positioned between the primary thermal conductivity spreader and a circuit board, wherein the secondary thermal conductivity spreader layer comprises a thermal conductivity spreader that is thermally coupled to the first heat-generating component and extends toward at least one additional heat-generating component having a lower thermal load than the first heat-generating component, wherein at least a portion of the secondary thermal conductivity spreader layer is disposed at a distance above the circuit board to define airflow channels.

Abstract: Methods of treating a plasma showerhead comprise placing a showerhead comprising a faceplate and a plurality of gas openings PECVD substrate processing chamber having a process volume between the substrate support and the faceplate, and then exposing the showerhead to a silicon-containing precursor and a reactant gas so that the process volume and the gas openings are filled with the silicon-containing precursor and the reactant gas. The method includes introducing a first plasma in the PECVD substrate processing chamber to form a silicon oxide thin film or a silicon nitride thin film on the lower surface of the faceplate and lining the gas openings. A precursor-removing purge gas is flowed and a second plasma is struck to densify the thin film.

Abstract: An IC device includes first and second bit circuits adjacent to each other along a row direction, third and fourth bit circuits adjacent to each other along the row direction, and a first column of output pins aligned in a column direction. The first and second bit circuits include first through fourth power rails and first through sixth active areas extending in the row direction, and the third and fourth bit circuits include the fourth power rail, fifth through seventh power rails, and seventh through twelfth active areas extending in the row direction. The first column of output pins includes first and second output pins adjacent to the second bit circuit and coupled to the respective first and second bit circuits and third and fourth output pins adjacent to the fourth bit circuit and coupled to the respective third and fourth bit circuits.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A data storage structure is arranged over the substrate and laterally between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the data storage structure. The first doped region is laterally between the isolation structure and the data storage structure. A remnant is arranged over and along a sidewall of the isolation structure. The remnant includes a first material having a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment.

Abstract: An endpoint framework is implemented for sharing one or more applications between one or more endpoint devices. To initiate sharing of an application, the system includes a first endpoint device running an application that generates notifications based on a condition or status of the application running. The first endpoint device provides these notifications to a second endpoint device which are output by the second endpoint device. The second endpoint device receives interactions with the output notifications and provides these interactions to the first endpoint device. In response to the interactions indicating the initiation of application sharing, the first endpoint device generates an application stream relating to the running application and provides it to the second endpoint device.

Abstract: A memory device has a memory cell operated in a first power domain having a first voltage level. A memory word line is connected to the memory cell, and a memory bit line is connected to the memory cell. A word line decoder circuit is operated in the first power domain, and a word line driver circuit is configured to receive a row address signal from the word line decoder circuit and output a word line enable signal to the memory word line. An IO circuit is connected to the memory bit line, and the IO circuit is operated in a second power domain having a second voltage level lower than the first voltage level. A tracking word line is connected to a tracking cell, and the tracking word line is configured to output a tracking cell enable signal in the first power domain. A tracking bit line is connected to the tracking cell, and the tracking bit line is configured to output a trigger signal in the first power domain to the IO circuit.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: Plasma showerhead assemblies are disclosed comprising a conductive plate having a plurality of the conductive plate openings, a dielectric faceplate having a thickness and a plurality of dielectric faceplate gas openings extending through the dielectric faceplate thickness in fluid communication with the plurality of the conductive plate gas openings. A conductive insert is disposed within at least one of the dielectric faceplate gas openings or adjacent o-rings included in the plasma showerhead assemblies.

Abstract: A first aspect of this disclosure is related to a computer-implemented method for identifying neuronal patterns in an image, comprising the steps: obtaining a first data set with Golgi-stained neuronal structures; based on the first data set, determining a first auxiliary data set, AR1, based on a first type of neuronal structure and a second auxiliary data set, AR2, based on a second type of neuronal structure; analyzing AR1 with a first method to identify information related to the first type of neuronal structure in AR1; analyzing AR2 with a second method to identify information related to the second type of neuronal structure in AR2; generating a second data set with the identified information related to the first and second type of neuronal structures.

Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A ferroelectric material is arranged over the substrate and between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the ferroelectric material. The isolation structure has a first width measured along an uppermost surface of the isolation structure and a second width measured along a horizontal line below the uppermost surface of the isolation structure. The second width is larger than the first width.

Abstract: A connecting cable includes an insulative seat, a circuit board, a protective cover and a spring. The insulative seat includes a body. The body is formed with a slot and a conducting opening. The circuit board includes a substrate and conductive portions. The substrate is inserted into the slot. The conductive portions are exposed from the conducting opening. The protective cover is disposed on the body to cover the conducting opening and slidable. The spring has one end abutting against the body and another end fixed on the protective cover. The conducting opening may be opened by pushing the protective cover by the counterpart connector to compress the spring. The protective cover may be returned back to an original position by an elastic force from the spring.

Abstract: The present disclosure provides a wafer chuck including a substrate and a heating/cooling wafer. The substrate includes a first surface facing a wafer to be carried and a second surface opposite to the first surface. The heating/cooling wafer is disposed on the first surface of the substrate and includes a plurality of heating/cooling units arranged in an array. In a direction perpendicular to the first surface, the positions of the heating/cooling units and the positions of a plurality of dies included in the wafer to be carried are corresponded with each other, and the heating/cooling units can heat or cool the corresponding dies individually.

Abstract: An electronic device is provided that implements thermally conductive plastic supports that may replace the typical use of “feet” used in conventional electronic devices. The thermally conductive supports may extend through the bottom chassis cover (e.g. the “D cover”) of the electronic device, and be mechanically and thermally coupled to a heat pipe that is in turn coupled to a heat source for which thermal regulation is utilized. The thermally conductive plastic supports may provide a heat path from the heat source to the bottom chassis cover and, when the electronic device is disposed on a surface, an additional heat path may be provided from the heat source to this surface.

Abstract: A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.

Abstract: A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for electronic devices with tactile keyboards. An example electronic device includes a tactile keyboard having a plurality of rows of keys; a printed circuit board; a first row of switches on the printed circuit board, a first row of the plurality of rows of keys to interact with the first row of switches; and a second row of switches on a component adjacent to the printed circuit board, a second row of the plurality of rows of keys to interact with the second row of switches.

Abstract: A method for forming an indium gallium nitride quantum well structure is disclosed. The method includes forming a gallium nitride microdisk on a substrate, with the gallium nitride microdisk having an inverted pyramid form and an end face; and forming multiple quantum well layers on the end face, with each quantum well layer including an indium gallium nitride quantum well and a barrier layer. The indium gallium nitride quantum well is grown at a growth temperature adjusted using a trend equation within a temperature range of 480° C. to 810° C.

Abstract: A tool, such as a tape measure, including a spring-based retraction system is shown. The spring-based retraction system is driven by a spiral spring, that has a variable preformed stress profile along the length of the spring.