Abstract: The semiconductor structure includes a first die structure including a first substrate, a first bonding dielectric disposed over the first substrate, and a first bonding pad surrounded by the first bonding dielectric; a second die structure including a second substrate, an isolation member extending into the second substrate, a second bonding dielectric bonded with the first bonding dielectric, and a second bonding pad surrounded by the second bonding dielectric and bonded with the first bonding pad; a dielectric member disposed over the second die structure; a conductive via extending through the dielectric member, the second substrate and the isolation member; and a conductive member disposed over the dielectric member and at least partially in contact with the conductive via, wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member.

Abstract: A Projected Capacitive (PCAP) display including multiple arrays of conductive electrodes performs a dual function. In a first function, the PCAP display uses the conductive electrode arrays to generate an electrostatic field and determines the presence and position of a conductive object based on small changes it detects in the capacitance of that electrostatic field. In a second function, the PCAP display uses the same conductive electrode arrays to generate a magnetic field. As a user swipes the card across the surface of the PCAP display, it causes small changes in the generated magnetic field. The PCAP display retrieves the data magnetically encoded onto the magnetic stripe card based on the changes it detects in the magnetic field.

Abstract: A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

Abstract: Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-? metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-? metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).

Abstract: An example redundant power supply system comprises a power supply input to receive power from a power supply; a buck-boost converter coupled to the power supply input; and a controller coupled to the buck-boost converter. The controller is to receive a power supply identification signal from the power supply. The controller is also to enable or disable the buck-boost converter based on the power supply identification signal.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A ferroelectric material is arranged over the substrate and between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the ferroelectric material. The isolation structure has a first width measured along an uppermost surface of the isolation structure and a second width measured along a horizontal line below the uppermost surface of the isolation structure. The second width is larger than the first width.

Abstract: A device includes a substrate, a first well region, a second well region, and a dummy region in the substrate, where the dummy region is a non-functional region situated between the first well region and the second well region. The first well region is configured to receive a first voltage and the second well region is configured to receive a second voltage that is different than the first voltage. The device further includes an active region that extends through at least part of the first well region and at least part of the dummy region, and at least one isolation structure situated in the dummy region between a first gate structure that extends over the active region in the dummy region on one side of the at least one isolation structure and a second gate structure on another side of the at least one isolation structure.

Abstract: Substrate support, substrate support assemblies and process chambers comprising same are described. The substrate support has a thermally conductive body with a top surface, a bottom surface and an outer edge, and a plurality of long edge purge channel outlet opening at the outer edge of the thermally conductive body. The substrate support is configured to support a substrate to be processed on a top surface of the substrate support. The top surface of the thermally conductive body may have a ceramic coating. Each of the plurality of purge channel outlet is in fluid communication with a long edge purge channel. The long edge purge channel is coated with a long edge purge channel coating. A substrate support assembly includes the substrate support and the support post coupled to the substrate support. The processing chamber include a chamber body and the substrate support within the chamber body.

Abstract: A tool, such as a tape measure, including a spring-based retraction system is shown. The spring-based retraction system is driven by a spiral spring, that has a variable preformed stress profile along the length of the spring.

Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

Abstract: A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A ferroelectric material is arranged over the substrate and laterally between the first doped region and the second doped region. A conductive electrode is over the ferroelectric material and between sidewalls of the ferroelectric material. One or more sidewall spacers are arranged along opposing sides of the ferroelectric material. A dielectric layer continuously and laterally extends from directly below the one or more sidewall spacers to directly below the ferroelectric material.

Abstract: A tool, such as a tape measure, including a spring-based retraction system is shown. The spring-based retraction system is driven by a spiral spring, that has a variable preformed stress profile along the length of the spring.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a polymer based enclosure, an absorber, and a connection interface. The polymer based enclosure is shaped to enclose a memory module connected to a memory module connection interface on a printed circuit board. The absorber is coated over the polymer based enclosure to block radio frequency signals generated by the memory modules. The connection interface is to connect to the memory module connection interface.

Abstract: A cleaning apparatus includes a stage, first annular closed-loop pipelines and first nozzles. The first annular closed-loop pipelines are located above the stage and have different outer diameters. A top-view pattern of the first annular closed-loop pipeline with a larger outer diameter surrounds a top-view pattern of the first annular closed-loop pipeline with a smaller outer diameter. The first nozzles are disposed on each of the first annular closed-loop pipelines.

Abstract: An assortment planning method, an assortment planning system and a processing apparatus thereof for a smart store are provided. The assortment planning system includes at least one tracking apparatus, a plurality of detecting apparatuses, and a processing apparatus. The tracking apparatus is used to identify a plurality of consumer tracks. The detecting apparatuses are used to detect a plurality of consumer interactive behaviors of a plurality of products. The processing apparatus includes a binding device, an intention analyzing device and an estimating device. The binding device is used to bind the consumer interactive behaviors with the consumer tracks to obtain a number of interactive behavior time sequence records. The intention analyzing device is used to obtain a plurality of consumption intentions for the products according to the interactive behavior time sequence records. The estimating device is used to estimate a best product combination according to the consumption intentions.

Abstract: An image sensing device that can adjust parameters of an image before sending it to a processor for reducing computing power and/or storage requirement is disclosed. The image sensing device includes an array of sensing pixels; an output amplifier; an analog-to-digital converter; a first set of registers and a second set of registers; an activation circuit; and a profiling logic. The profiling logic conducts statistical analysis on output data and adjusts parameters stored in the first set of registers until results of the statistical analysis reaches a target standard, wherein the adjusted parameters are used to generate an output image by each sensing pixel of the array of sensing pixels once the target standard is reached and a notification signal is sent to an external device for notifying the failure of parameter adjustment if the target standard fails to be reached within a predetermined times of adjustment.

Abstract: Processing methods described herein comprise forming a metal gate film on a narrow feature and a wide feature and depositing a hard mask on the metal gate film. The hard mask forms on the metal gate film at a top, bottom and sidewalls of the wide feature and on a top of the narrow feature to cover the metal gate film. Some processing methods comprise oxidizing the metal gate film on the narrow feature to convert a portion of the metal gate film to a metal oxide film. Some processing methods comprise etching the metal oxide film from the narrow feature to leave a gradient etch profile. Some processing methods comprise filling the narrow feature and the wide feature with a gap fill material comprising one or more of a metal nitride, titanium nitride (TiN) or titanium oxynitride (TiON), the gap fill material substantially free of seams and voids.