Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

Abstract: Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-? metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-? metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).

Abstract: An example redundant power supply system comprises a power supply input to receive power from a power supply; a buck-boost converter coupled to the power supply input; and a controller coupled to the buck-boost converter. The controller is to receive a power supply identification signal from the power supply. The controller is also to enable or disable the buck-boost converter based on the power supply identification signal.

Abstract: A device includes a substrate, a first well region, a second well region, and a dummy region in the substrate, where the dummy region is a non-functional region situated between the first well region and the second well region. The first well region is configured to receive a first voltage and the second well region is configured to receive a second voltage that is different than the first voltage. The device further includes an active region that extends through at least part of the first well region and at least part of the dummy region, and at least one isolation structure situated in the dummy region between a first gate structure that extends over the active region in the dummy region on one side of the at least one isolation structure and a second gate structure on another side of the at least one isolation structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A ferroelectric material is arranged over the substrate and between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the ferroelectric material. The isolation structure has a first width measured along an uppermost surface of the isolation structure and a second width measured along a horizontal line below the uppermost surface of the isolation structure. The second width is larger than the first width.

Abstract: Substrate support, substrate support assemblies and process chambers comprising same are described. The substrate support has a thermally conductive body with a top surface, a bottom surface and an outer edge, and a plurality of long edge purge channel outlet opening at the outer edge of the thermally conductive body. The substrate support is configured to support a substrate to be processed on a top surface of the substrate support. The top surface of the thermally conductive body may have a ceramic coating. Each of the plurality of purge channel outlet is in fluid communication with a long edge purge channel. The long edge purge channel is coated with a long edge purge channel coating. A substrate support assembly includes the substrate support and the support post coupled to the substrate support. The processing chamber include a chamber body and the substrate support within the chamber body.

Abstract: A tool, such as a tape measure, including a spring-based retraction system is shown. The spring-based retraction system is driven by a spiral spring, that has a variable preformed stress profile along the length of the spring.

Abstract: A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.

Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A ferroelectric material is arranged over the substrate and laterally between the first doped region and the second doped region. A conductive electrode is over the ferroelectric material and between sidewalls of the ferroelectric material. One or more sidewall spacers are arranged along opposing sides of the ferroelectric material. A dielectric layer continuously and laterally extends from directly below the one or more sidewall spacers to directly below the ferroelectric material.

Abstract: A tool, such as a tape measure, including a spring-based retraction system is shown. The spring-based retraction system is driven by a spiral spring, that has a variable preformed stress profile along the length of the spring.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a polymer based enclosure, an absorber, and a connection interface. The polymer based enclosure is shaped to enclose a memory module connected to a memory module connection interface on a printed circuit board. The absorber is coated over the polymer based enclosure to block radio frequency signals generated by the memory modules. The connection interface is to connect to the memory module connection interface.

Abstract: A cleaning apparatus includes a stage, first annular closed-loop pipelines and first nozzles. The first annular closed-loop pipelines are located above the stage and have different outer diameters. A top-view pattern of the first annular closed-loop pipeline with a larger outer diameter surrounds a top-view pattern of the first annular closed-loop pipeline with a smaller outer diameter. The first nozzles are disposed on each of the first annular closed-loop pipelines.

Abstract: An assortment planning method, an assortment planning system and a processing apparatus thereof for a smart store are provided. The assortment planning system includes at least one tracking apparatus, a plurality of detecting apparatuses, and a processing apparatus. The tracking apparatus is used to identify a plurality of consumer tracks. The detecting apparatuses are used to detect a plurality of consumer interactive behaviors of a plurality of products. The processing apparatus includes a binding device, an intention analyzing device and an estimating device. The binding device is used to bind the consumer interactive behaviors with the consumer tracks to obtain a number of interactive behavior time sequence records. The intention analyzing device is used to obtain a plurality of consumption intentions for the products according to the interactive behavior time sequence records. The estimating device is used to estimate a best product combination according to the consumption intentions.

Abstract: An image sensing device that can adjust parameters of an image before sending it to a processor for reducing computing power and/or storage requirement is disclosed. The image sensing device includes an array of sensing pixels; an output amplifier; an analog-to-digital converter; a first set of registers and a second set of registers; an activation circuit; and a profiling logic. The profiling logic conducts statistical analysis on output data and adjusts parameters stored in the first set of registers until results of the statistical analysis reaches a target standard, wherein the adjusted parameters are used to generate an output image by each sensing pixel of the array of sensing pixels once the target standard is reached and a notification signal is sent to an external device for notifying the failure of parameter adjustment if the target standard fails to be reached within a predetermined times of adjustment.

Abstract: The present invention discloses an monoclonal antibody, which can bind to HyIL-6 with the binding constant 2.86×10?10 and significantly inhibit IL-6/IL-6R/gp130 complex formation. In addition, the monoclonal antibody of the present invention effectively inhibits HyIL-6-stimulated signal transducer and activator of transcription 3(STAT3) activation and related vascular endothelial growth factor (VEGF) induction. Data from hydrogen deuterium exchange mass spectrometry (HDX-MS) demonstrate that the antibody of the present invention mainly binds to site IIIa of IL-6 and blocks the final step in the interaction between gp130 and IL-6/IL-6R complex. Additionally, data from ELISA binding assays and kinetics assays indicate that the antibody of the present invention interacts simultaneously with IL-6 and IL-6R, while it does not interact with IL-6R alone.

Abstract: Processing methods described herein comprise forming a metal gate film on a narrow feature and a wide feature and depositing a hard mask on the metal gate film. The hard mask forms on the metal gate film at a top, bottom and sidewalls of the wide feature and on a top of the narrow feature to cover the metal gate film. Some processing methods comprise oxidizing the metal gate film on the narrow feature to convert a portion of the metal gate film to a metal oxide film. Some processing methods comprise etching the metal oxide film from the narrow feature to leave a gradient etch profile. Some processing methods comprise filling the narrow feature and the wide feature with a gap fill material comprising one or more of a metal nitride, titanium nitride (TiN) or titanium oxynitride (TiON), the gap fill material substantially free of seams and voids.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: An intelligent storage device and an intelligent storage method are provided. The intelligent storage device includes a storage space, an infrared sensor, a weight sensor, a transceiver, and a processor. The storage space is suitable for storing an object. The infrared sensor senses the storage space to generate infrared sensing data. The weight sensor senses the object in the storage space to generate weight sensing data. The processor is coupled to the infrared sensor, the weight sensor, and the transceiver, determines whether the object is placed in or removed from the storage space according to the infrared sensing data and the weight sensing data to generate an event record, and transmits the event record via the transceiver.

Abstract: An intelligent store system and an intelligent store method are provided. The method includes: sensing, by a proximity sensor, whether there is a first customer approaching the proximity sensor; sensing, by an image sensor, a movement trajectory of the first customer; and determining whether the first customer is entering or leaving a store in response to the first customer approaching the proximity sensor sensed by the proximity sensor. If the first customer is entering the store, a first virtual identity and a first virtual shopping cart corresponding to the first virtual identity are generated for the first customer, and a first product list of the first virtual shopping cart is updated according to the movement trajectory. If the first customer is leaving the store, a first operation of the first customer is received by a human machine interface, and the first product list according to the first operation is updated.