Patents by Inventor Chi Chou

Chi Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11530900
    Abstract: A sighting system includes a sight body, a compensating mechanism, a converting unit, a processing unit and an output unit. The sight body is configured to aim an object. The compensating mechanism is disposed on the sight body and includes a base, an adjusting unit and an adjusting cap, wherein the adjusting cap is configured to rotate the adjusting unit with respect to the base. The converting unit is disposed in the compensating mechanism and is configured to obtain rotation information of the adjusting cap, convert the rotation information into an electrical signal and output the electrical signal. The processing unit is configured to receive the electrical signal for obtaining an instant adjusting value of the adjusting cap and to compare the instant adjusting value with a predetermined adjusting value. The output unit is electrically connected to the processing unit for presenting information for correction of bullet impact points.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 20, 2022
    Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventors: Hung-Chi Chou, Chia-Kan Chang, Chia-Chi Tang
  • Patent number: 11508661
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Publication number: 20220359508
    Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Pin-Dai SUE, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Ya-Chi CHOU, Chi-Yu LU
  • Patent number: 11392820
    Abstract: A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: July 19, 2022
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Jian-Wei Su, Yen-Chi Chou, Ru-Hui Liu
  • Publication number: 20220189975
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: Chih-Jung NI, Chuan-Chi CHOU, Yao-Ting TSAI
  • Patent number: 11355391
    Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 7, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Feiyue Ma, Kai Wu, Yu Lei, Kazuya Daito, Yi Xu, Vikash Banthia, Mei Chang, He Ren, Raymond Hoiman Hung, Yakuan Yao, Avgerinos V. Gelatos, David T. Or, Jing Zhou, Guoqiang Jian, Chi-Chou Lin, Yiming Lai, Jia Ye, Jenn-Yue Wang
  • Publication number: 20220138838
    Abstract: An intelligent store system and an intelligent store method are provided. The method includes: sensing, by a proximity sensor, whether there is a first customer approaching the proximity sensor; sensing, by an image sensor, a movement trajectory of the first customer; and determining whether the first customer is entering or leaving a store in response to the first customer approaching the proximity sensor sensed by the proximity sensor. If the first customer is entering the store, a first virtual identity and a first virtual shopping cart corresponding to the first virtual identity are generated for the first customer, and a first product list of the first virtual shopping cart is updated according to the movement trajectory. If the first customer is leaving the store, a first operation of the first customer is received by a human machine interface, and the first product list according to the first operation is updated.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 5, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chi-Chou Chiang, Hsin-Chien Huang, Wen Tsui, Yu Cho
  • Publication number: 20220137256
    Abstract: An intelligent storage device and an intelligent storage method are provided. The intelligent storage device includes a storage space, an infrared sensor, a weight sensor, a transceiver, and a processor. The storage space is suitable for storing an object. The infrared sensor senses the storage space to generate infrared sensing data. The weight sensor senses the object in the storage space to generate weight sensing data. The processor is coupled to the infrared sensor, the weight sensor, and the transceiver, determines whether the object is placed in or removed from the storage space according to the infrared sensing data and the weight sensing data to generate an event record, and transmits the event record via the transceiver.
    Type: Application
    Filed: December 15, 2020
    Publication date: May 5, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Chien Huang, Po-Yuan Hsiao, Chu-An Chung, Wen Tsui, Chi-Chou Chiang
  • Publication number: 20220140732
    Abstract: An example redundant power supply system comprises a power supply input to receive power from a power supply; a buck-boost converter coupled to the power supply input; and a controller coupled to the buck-boost converter. The controller is to receive a power supply identification signal from the power supply. The controller is also to enable or disable the buck-boost converter based on the power supply identification signal.
    Type: Application
    Filed: July 23, 2019
    Publication date: May 5, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Ying-Chi Chou, Feng Ming Lu, Chien Fa Huang, Chieh-Shen Huang, Tsung Yen Chen, Peter Seiler, Poying Chih
  • Publication number: 20220132053
    Abstract: An image sensing device that can adjust parameters of an image before sending it to a processor for reducing computing power and/or storage requirement is disclosed. The image sensing device includes an array of sensing pixels; an output amplifier; an analog-to-digital converter; a first set of registers and a second set of registers; an activation circuit; and a profiling logic. The profiling logic conducts statistical analysis on output data and adjusts parameters stored in the first set of registers until results of the statistical analysis reaches a target standard, wherein the adjusted parameters are used to generate an output image by each sensing pixel of the array of sensing pixels once the target standard is reached and a notification signal is sent to an external device for notifying the failure of parameter adjustment if the target standard fails to be reached within a predetermined times of adjustment.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Inventors: Chi-Chou Lin, Zheng-Ping He
  • Patent number: 11302705
    Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 12, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chih-Jung Ni, Chuan-Chi Chou, Yao-Ting Tsai
  • Publication number: 20220098731
    Abstract: Methods of forming electronic devices comprising tungsten film stacks are provided. Methods include forming a tungsten nucleation layer on the barrier layer using an atomic layer deposition (ALD) process including a tungsten precursor that is free of fluorine. Forming the nucleation layer comprises controlling process parameters and/or forming WSi pre-nucleation layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Kedi Wu, Chenfei Shen, Chi-Chou Lin, Ilanit Fisher, Shih Chung Chen, Mandyam Sriram, Srinivas Gandikota
  • Patent number: 11282988
    Abstract: A light-emitting device includes a composite structure having a phosphor crystal sheet and phosphor crystal powders on the phosphor crystal sheet. A light-emitting unit of the device is disposed under a side of the phosphor crystal sheet that is opposite to a side of the phosphor crystal powders. A problem of blue-enriched white light may be tackled.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 22, 2022
    Assignees: TAIWAN APPLIED CRYSTAL CO., LTD., NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Tsung-Xian Lee, Chu-An Lee, Wei-Chang Lin, Ming-Chi Chou
  • Publication number: 20220064785
    Abstract: Embodiments of the present disclosure generally relate chamber lids and methods of using such for gas-phase particle reduction. In an embodiment is provided a chamber lid that includes a top wall, a bottom wall, a plurality of vertical sidewalls, and an interior volume within the chamber lid defined by the top wall, the bottom wall, and the plurality of vertical sidewalls. The chamber lid further includes a plurality of air flow apertures, wherein the plurality of air flow apertures is configured to fluidly communicate air into the interior volume and out of the interior volume, and a mesh disposed on a face of at least one of the air flow apertures of the plurality of air flow apertures. In another embodiment is provided a method of processing a substrate in a substrate processing chamber, the substrate processing chamber comprising a chamber lid as described herein.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Inventors: Muhannad MUSTAFA, Haoyan SHA, Muhammad M. RASHEED, Chi-Chou LIN, Mario D. SILVETTI, Bin CAO, Shihchung CHEN, Yongjing LIN
  • Publication number: 20220047857
    Abstract: A manufacturing method for a micro-needle device includes following steps: a target tissue basic information obtaining step, a micro-needle template obtaining step, a micro-needle material adding step, a micro-needle semi-product obtaining step, and a micro-needle device obtaining step. The inner tissue distribution information is obtained by the application of optical coherence tomography. The micro-needle template is obtained according to the skin surface curvature information and the inner tissue distribution information. The micro-needle template has a plurality of areas and a plurality of mold holes. One or both of the diameter and the depth of the mold hole is determined by the inner tissue distribution information, and the curvature radius of the areas is determined by the skin surface curvature information. The manufacturing method for a micro-needle device is applicable to micro-needles with mixed configurations as well as micro-needles with syringe configurations.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 17, 2022
    Applicant: Tamkang University
    Inventors: Ming-Kai Chern, Man-Piu Chan, Yueh-Tzu Lo, I-Chang Liu, Shih-Ting Lin, You-Lin Wei, Wen-Chi Chou, Wen-Hua Chuang, Yin-Jun Wu, Hun-Boa Wang, Bo-Cheng Wang
  • Publication number: 20220044714
    Abstract: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Meng-Fan CHANG, Yen-Chi CHOU, Jian-Wei SU
  • Publication number: 20210384036
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 9, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Chi-Chou Lin, Kedi Wu, Wen Ting Chen, Shih Chung Chen, Srinivas Gandikota, Mandyam Sriram, Chenfei Shen, Naomi Yoshida, He Ren
  • Publication number: 20210384035
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a fluorine-free metallic tungsten film. The fluorine-free metallic tungsten film is exposed to a second process condition to deposit a tungsten film on the fluorine-free metallic tungsten film.
    Type: Application
    Filed: April 8, 2021
    Publication date: December 9, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Shih Chung Chen, Kedi Wu, Ashley Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Mandyam Sriram, Wen Ting Chen, Srinivas Gandikota, Chenfei Shen, Naomi Yoshida, He Ren
  • Patent number: 11187721
    Abstract: An electronic device having a structure that electrically connects the contactor to an electronic device during a testing process is disclosed. The contactor includes a holder for accommodating the electronic device during the testing process; a flexible circuit, having a first set of contacts electrically connected to the corresponding electrode terminals of the electronic device, and a second set of contacts electrically connected to a control unit that sends test signals during the test process; an elastomer, for adjusting the pressure between the first set of contacts of the flexible circuit and the corresponding electrode terminals of the electronic device while being pressed together; and an alignment tool, for aligning the first set of contacts with the corresponding electrode terminals of the electronic device. The electrode terminals of the electronic device are located on the same surface of the electronic device and the flexible circuit is detachable from the contactor.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 30, 2021
    Assignee: SunASIC Technologies, Inc.
    Inventors: Chi-Chou Lin, Hsien-Hsueh Lee, Zheng-Ping He
  • Publication number: 20210356630
    Abstract: The present invention relates to a manufacturing method for a mid-infrared lens, which includes the following steps: placing a lens in the path of a far-infrared radiation source, enabling the lens to receive the far infrared rays; immersing the lens in a hardening liquid, causing the hardening liquid to coat the lens, wherein the hardening liquid is an intermixture of silicone and isopropanol or an intermixture of silicone and methanol, and a far-infrared material or a far-infrared composite material is additionally added to the hardening liquid; placing the lens coated with the hardening liquid in a drying space to dry, causing the hardening liquid to dry and harden and form a hardened layer on the surface of the lens. The temperature of the drying space lies between 80 and 120° C., and the drying time lies between 1 and 10 hours.
    Type: Application
    Filed: March 25, 2021
    Publication date: November 18, 2021
    Inventor: CHI-CHOU YUAN