Patents by Inventor Chi Hsieh

Chi Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9997447
    Abstract: A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of substantially parallel top-side metal bars, and a plurality of substantially parallel bottom-side metal bars. The first insulation layer is on the carrier and has a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes. The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode. The plurality of interconnection structures are within the through holes and formed as conductive through holes. The plurality of substantially parallel top-side metal bars are on the first surface of the first insulation layer. The plurality of substantially parallel bottom-side metal bars are on the second surface of the first insulation layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 12, 2018
    Assignee: ADVANCED SSEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Hung-Yi Lin, Sheng-Chi Hsieh
  • Patent number: 9960781
    Abstract: A current-mode analog-digital conversion (ADC) circuit directly samples and digitizes an input signal in the current domain; the input signal may be a current signal or a photonic signal. Input capacitors may be coupled to the current source by a series of switches and configured to store a target charge. The target charge may be compared to a reference voltage by comparators of the system to generate digital output. The current-mode ADC circuit may be adapted to flash, successive-approximation, and pipeline architectures, or embodied in a photonic receiver incorporating current-mode ADC circuits configured to sample and digitize photonic signals.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 1, 2018
    Assignee: Rockwell Collins, Inc.
    Inventors: Wenlu Chen, Han Chi Hsieh, Raymond Zanoni
  • Patent number: 9950077
    Abstract: The present disclosure provides anti-folate receptor alpha (FRA) antibody-drug conjugates comprising a hydrophilic self-immolative linker. The present disclosures further provide compositions and methods for treating cancers.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 24, 2018
    Assignees: BIOALLIANCE C.V., ABGENOMICS INTERNATIONAL INC.
    Inventors: Rong-Hwa Lin, Shih-Yao Lin, Yu-Chi Hsieh, Chiu-Chen Huang, Shu-Hua Lee, Yu-Ying Tsai, Feng-Lin Chiang, Li-An Hu
  • Patent number: 9943610
    Abstract: The present disclosure provides compounds with a hydrophilic self-immolative linker, which is cleavable under appropriate conditions and incorporates a hydrophilic group to provide better solubility of the compound. The compounds of the present disclosure comprise a drug moiety, a targeting moiety capable of targeting a selected cell population, and a linker which contains an acyl unit, an optional spacer unit for providing distance between the drug moiety and the targeting moiety, a peptide linker which can be cleavable under appropriate conditions, a hydrophilic self-immolative linker, and an optional second self-immolative spacer or cyclization self-elimination linker.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 17, 2018
    Assignees: BioAlliance C.V., AbGenomics International Inc.
    Inventors: Rong-Hwa Lin, Shih-Yao Lin, Yu-Chi Hsieh, Chiu-Chen Huang
  • Patent number: 9906200
    Abstract: A power filter is provided, including a circuit board module, an insulating base, several connect terminals, and an inductor. The circuit board module includes a circuit board and several electronic components, wherein the circuit board forms several connect holes thereon and the electronic components are electrically connected to the circuit board. The connect terminals are fixed on the insulating base and each has a connecting part and a clamping part, wherein the connecting parts are joined with the connect holes of the circuit board. The inductor includes at least one wire with both terminals clamped by the clamping parts, and the wire is electrically connected to the circuit board module through the connecting parts.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 27, 2018
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shin-Chih Hsieh, Po-Jen Tsai, Chia-Chi Hsieh
  • Patent number: 9881917
    Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: January 30, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Chiang Shih, Sheng-Chi Hsieh, Chien-Hua Chen, Teck-Chong Lee
  • Publication number: 20180012853
    Abstract: A chip package includes a chip, an isolation layer on the bottom surface and the sidewall, a redistribution layer that is on the isolation layer and in electrical contact with a side surface of the conductive pad, and a passivation layer. The chip has a sensor, at least one conductive pad, a top surface, a bottom surface, and a sidewall. The sensor is located on the top surface. The conductive pad is located on an edge of the top surface. The redistribution layer at least partially protrudes from the conductive pad so as to be exposed. The passivation layer is located on the isolation layer and the redistribution layer, such that the redistribution layer not protruding from the conductive pad is between the passivation layer and the isolation layer, and the redistribution layer protruding from the conductive pad is located on the passivation layer.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 11, 2018
    Inventors: Hsi-Chien LIN, Jyh-Wei CHEN, Jun-Chi HSIEH, Yue-Ting CHEN
  • Patent number: 9797838
    Abstract: This present invention relates to a screening method for rapidly identifying the hybridomas upon cell size and the expression of an exogenous label such as fluorescence labeling. This method of this present invention can largely shortens the time cost for antibody development by saving the time period with comparison of traditional methods using cell culture with media such as HAT medium.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 24, 2017
    Assignee: TUNGHAI UNIVERSITY
    Inventors: Chang-Chi Hsieh, Ming-Shiou Jan, Ai Shih, Chuan-Kai Chou, Yen-Wan Hsiao, Ying-Chun Lai
  • Publication number: 20170229393
    Abstract: A semiconductor device includes a substrate and at least one inductor on the substrate. The inductor includes top portions separated from one another, bottom portions separated from one another, and side portions separated from one other. Each side portion extends between one of the top portions and one of the bottom portions. A semiconductor device includes a substrate, a first patterned conductive layer on the substrate, a second patterned conductive layer, and at least one dielectric layer between the first patterned conductive layer and the second patterned conductive layer. The first patterned conductive layer defines bottom crossbars separated from each other, each bottom crossbar including a bend angle. The second patterned conductive layer defines top crossbars separated from each other, wherein each top crossbar is electrically connected to a bottom crossbar.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 10, 2017
    Inventors: Sheng-Chi HSIEH, Chih-Pin HUNG
  • Patent number: 9674983
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include heat-rejecting media thermally coupled to one or more information handling resources, a connector for receiving a modular information handling resource, the connector having a latch for facilitating insertion or removal of the modular information handling resource to or from the connector, and a removable baffle for directing a flow of air proximate to the heat-rejecting media. The removable baffle may have two substantially planar sides and an edge substantially perpendicular to the two planar sides, such that when the removable baffle is located within a chassis including the heat-rejecting media and the connector, the latch engages with the edge to mechanically maintain a location of the removable baffle within the chassis.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: June 6, 2017
    Assignee: Dell Products L.P.
    Inventors: Chin-An Huang, Chen-Fa Wu, Shin-Chi Hsieh
  • Publication number: 20170140451
    Abstract: In one aspect, this application describes a method for determining a version of a software application targeted for a computing device. The method includes receiving, at an application marketplace system and from a user associated with a computing device that operates remotely from the application marketplace system, a request that corresponds to a software application distributed by the application marketplace system, the software application having multiple versions on the application marketplace system. The method also includes determining one or more device attributes that are associated with the computing device, and identifying a particular version of the software application, from among the multiple versions on the application marketplace system, that is targeted for the computing device based on the device attributes. The method also includes providing, for display to the user and in response to the request, information related to the particular version of the software application.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Ilya Firman, Jasper S. Lin, Mark D. Womack, Yu-Kuan Lin, Sheng-chi Hsieh, Juliana Tsang
  • Publication number: 20170127562
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include heat-rejecting media thermally coupled to one or more information handling resources, a connector for receiving a modular information handling resource, the connector having a latch for facilitating insertion or removal of the modular information handling resource to or from the connector, and a removable baffle for directing a flow of air proximate to the heat-rejecting media. The removable baffle may have two substantially planar sides and an edge substantially perpendicular to the two planar sides, such that when the removable baffle is located within a chassis including the heat-rejecting media and the connector, the latch engages with the edge to mechanically maintain a location of the removable baffle within the chassis.
    Type: Application
    Filed: November 2, 2015
    Publication date: May 4, 2017
    Inventors: Chin-An Huang, Chen-Fa Wu, Shin-Chi Hsieh
  • Patent number: 9595027
    Abstract: In one aspect, this application describes a method for determining a version of a software application targeted for a computing device. The method includes receiving, at an application marketplace system and from a user associated with a computing device that operates remotely from the application marketplace system, a request that corresponds to a software application distributed by the application marketplace system, the software application having multiple versions on the application marketplace system. The method also includes determining one or more device attributes that are associated with the computing device, and identifying a particular version of the software application, from among the multiple versions on the application marketplace system, that is targeted for the computing device based on the device attributes. The method also includes providing, for display to the user and in response to the request, information related to the particular version of the software application.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 14, 2017
    Assignee: Google Inc.
    Inventors: Ilya Firman, Jasper S. Lin, Mark D. Womack, Yu-Kuan Lin, Sheng-chi Hsieh, Juliana Tsang
  • Patent number: 9577370
    Abstract: A high-speed electrical connector includes an insulating case, several signal terminals, several grounding terminals, an electrical bridge, and several resilient conductive buffers mounted in the insulating case. Each of the signal and grounding terminals has a fixing segment and a swing segment swingable with respect to the fixing segment. The electrical bridge corresponds to two of the grounding terminals. The conductive buffers are disposed on the electrical bridge and are respectively arranged in the swing paths of the swing segments. Each conductive buffer is configured to transform from an initial state to a deformation state by pressing. Each swing segment can swing to press the corresponding conductive buffer, causing the corresponding conductive buffer to be in the deformation state, thereby establishing an electrical connection path between the electrical bridge and the corresponding grounding terminals. In one example, the buffer can be formed of elastomer mixed with conductive particles.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: February 21, 2017
    Assignee: GREENCONN CORP.
    Inventors: Han-Nien Lin, Tung-Chi Hsieh, Keh-Chang Cheng
  • Publication number: 20170047276
    Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the same. The semiconductor device package comprises a substrate, a first patterned conductive layer, an insulator layer, a second patterned conductive layer, and a dielectric layer. The first patterned conductive layer is disposed on a surface of the substrate. The insulator layer is disposed on the surface of the substrate and covers the first patterned conductive layer. The second patterned conductive layer is fully encapsulated by the insulator layer. The dielectric layer is disposed on the insulator layer.
    Type: Application
    Filed: August 13, 2015
    Publication date: February 16, 2017
    Inventors: Chien-Hua CHEN, Teck-Chong LEE, Chi-Han CHEN, Sheng-Chi HSIEH
  • Publication number: 20170018550
    Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 19, 2017
    Inventors: Hsu-Chiang SHIH, Sheng-Chi HSIEH, Chien-Hua CHEN, Teck-Chong LEE
  • Publication number: 20160344134
    Abstract: A high-speed electrical connector includes an insulating case, several signal terminals, several grounding terminals, at least one electrical bridge, and several resilient conductive buffers, which are mounted in the insulating case. Each one of the signal and grounding terminals has a fixing segment and a swing segment swingable with respect to the fixing segment. The electrical bridge corresponds to at least two of the grounding terminals. The conductive buffers are disposed on the electrical bridge and are respectively arranged in the swing paths of the swing segments of the grounding terminals. Each conductive buffer is configured to transform from an initial state to a deformation state by pressing. Each swing segment can swing to press the corresponding conductive buffer, causing the corresponding conductive buffer to be in the deformation state, thereby establishing an electrical connection path between the electrical bridge and the corresponding grounding terminals.
    Type: Application
    Filed: October 16, 2015
    Publication date: November 24, 2016
    Inventors: HAN-NIEN LIN, TUNG-CHI HSIEH, KEH-CHANG CHENG
  • Patent number: 9459863
    Abstract: Applications that have been designed for a smaller format device such as a smartphone and simply ported to a larger format device such as a tablet can be discerned from applications designed specifically for the larger format device. An application can be evaluated based on tablet compatibility criteria and can be assigned a tablet compatibility score. The application can be evaluated based on quality criteria and can be assigned a quality score. The compatibility score and the quality score can be used to help find and rate any number of applications.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: October 4, 2016
    Assignee: Google Inc.
    Inventors: Alec Go, Sheng Chi Hsieh, Atul Kumar, Kenneth Lui, Nicolaus Todd Mote
  • Publication number: 20160276998
    Abstract: A power filter is provided, including a circuit board module, an insulating base, several connect terminals, and an inductor. The circuit board module includes a circuit board and several electronic components, wherein the circuit board forms several connect holes thereon and the electronic components are electrically connected to the circuit board. The connect terminals are fixed on the insulating base and each has a connecting part and a clamping part, wherein the connecting parts are joined with the connect holes of the circuit board. The inductor includes at least one wire with both terminals clamped by the clamping parts, and the wire is electrically connected to the circuit board module through the connecting parts.
    Type: Application
    Filed: November 2, 2015
    Publication date: September 22, 2016
    Inventors: SHIN-CHIH HSIEH, PO-JEN TSAI, CHIA-CHI HSIEH
  • Publication number: 20160258957
    Abstract: This present invention relates to a screening method for rapidly identifying the hybridomas upon cell size and the expression of an exogenous label such as fluorescence labeling. This method of this present invention can largely shortens the time cost for antibody development by saving the time period with comparison of traditional methods using cell culture with media such as HAT medium.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 8, 2016
    Inventors: Chang-Chi HSIEH, Ming-Shiou JAN, Ai SHIH, Chuan-Kai CHOU, Yen-Wan HSIAO, Ying-Chun LAI