Patents by Inventor Chi-I Lang

Chi-I Lang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260168102
    Abstract: A method of forming a low-k dielectric layer with barrier properties is disclosed. The method includes forming a dielectric layer by plasma enhanced chemical vapor deposition (PECVD) with the addition of hydrogen (H2) gas during the process. The addition of hydrogen (H2) during the PECVD process provides a low-k barrier layer with increased density.
    Type: Application
    Filed: December 13, 2024
    Publication date: June 18, 2026
    Applicant: Applied Materials, Inc.
    Inventors: Kent Zhao, Albert Kim, Bo Xie, Chi-I Lang, Li-Qun Xia
  • Publication number: 20260136851
    Abstract: Exemplary methods of semiconductor processing may include providing a silicon-free treatment precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. An exposed region of a silicon-containing material and an exposed region of a metal-containing material may be disposed on the substrate. The methods may include contacting the substrate with the silicon-free treatment precursor. The contacting may reduce a dielectric constant of the silicon-containing material. Subsequent to contacting the substrate with the silicon-free treatment precursor, a surface of the metal-containing material may be silicon-free.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 14, 2026
    Applicant: Applied Materials, Inc.
    Inventors: Jingyi Sui, Xinyi Lu, Bo Xie, Chi-I Lang, Li-Qun Xia
  • Publication number: 20260136853
    Abstract: Exemplary methods of semiconductor processing may include providing a treatment precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. An exposed region of a silicon-containing material and an exposed region of a metal-containing material may be disposed on the substrate. The methods may include contacting the substrate with the treatment precursor. The contacting may increase an amount of methyl groups (—CH3) in the silicon-containing material. The methods may include performing a wet clean to remove a silicon-containing residue from the metal-containing material.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 14, 2026
    Applicant: Applied Materials, Inc.
    Inventors: Xinyi Lu, Bo Xie, Chi-I Lang, Han Wang, Tam Kevin Do, Biao Liu, Li-Qun Xia, Shinjae Kwon, Srinivas Guggilla, Balasubramanian Pranatharthiharan
  • Publication number: 20260114254
    Abstract: A surface recovery process that restores the hydrophobicity of dielectric surfaces and promotes selective deposition of metal-fill such as molybdenum onto metal-containing surfaces while reducing or preventing growth on the dielectric surfaces. Additionally, the surface recovery process reduces film loss against subsequent wet etching processes such as DHF. The recovery precursor soak is performed with optional UV (concurrent or sequential) to react with silanols on damaged dielectric surface to replenish —CH3 and recover hydrophobicity of the dielectric surface. The recovery precursor is a carbon-containing recovery precursor, for example, organohalosilanes, esters, silyl ethers, organoaminosilanes, silyl esters, hydrocarbons, or a combination thereof.
    Type: Application
    Filed: October 1, 2025
    Publication date: April 23, 2026
    Inventors: Xinyi LU, Kent Qiujing ZHAO, Bo XIE, Chi-I LANG, Li-Qun XIA
  • Publication number: 20260101830
    Abstract: Embodiments described herein generally relate to processes for back end of line advanced packaging assembly. More particularly, embodiments described herein relate to processes for activating silicon surfaces for hydrophilic silicon direct bonding applications. In at least one embodiment, a method for activating a substrate is provided. The method includes providing a substrate into a process chamber, the substrate including a plurality of patterned structures, at least one metal layer and a silicon surface, and curing the silicon surface of the substrate. The curing process includes flowing one or more gases into the process chamber, the one or more gases including ozone, and providing UV light while operating the process chamber at a temperature of about 25° C. to about 300° C. A plurality of oxygen radicals are formed from the ozone and reacted with the silicon surface of the substrate to form an activated surface.
    Type: Application
    Filed: October 1, 2025
    Publication date: April 9, 2026
    Inventors: Xinyi LU, Han WANG, Bo XIE, Monika Halim JAMIESON, Chi-I LANG, Li-Qun XIA
  • Patent number: 12550647
    Abstract: A method of forming features over a semiconductor substrate is provided. The method includes supplying a gas mixture over a surface of a substrate at a continuous flow rate. A first radio frequency (RF) signal is delivered to an electrode while the gas mixture is supplied at the continuous flow rate to deposit a polymer layer over the surface of the substrate. The surface of the substrate includes an oxide containing portion and a nitride containing portion. A second RF signal is delivered to the electrode while continuously supplying the gas mixture at the continuous flow rate to selectively etch the oxide containing portion relative to the nitride containing portion.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: February 10, 2026
    Assignee: Applied Materials, Inc.
    Inventors: Lei Liao, Yung-chen Lin, Chi-I Lang, Ho-yung David Hwang
  • Publication number: 20260040847
    Abstract: A method for processing a substrate is provided. The method includes disposing a substrate in a processing region of a process chamber and flowing a silicon containing precursor gas into the processing region. The method also includes exposing the precursor gas to only plasma radicals and non-charged species generated from an inert gas plasma to deposit a low-k film on the substrate, wherein the low-k film comprises preserved bonds of one or more silicon containing functional groups from the one or more silicon containing precursors of the precursor gas.
    Type: Application
    Filed: August 2, 2024
    Publication date: February 5, 2026
    Inventors: Tzu-Yu OU, Bo XIE, Chi-I LANG, Li-Qun XIA, Chidambara A. RAMALINGAM, Shankar VENKATARAMAN
  • Publication number: 20260018409
    Abstract: The present disclosure generally provides methods. The methods include exposing a substrate in a processing chamber to a deposition precursor to form a first film. The first film having a first dielectric constant, a first leakage current, a first breakdown voltage, and a first hardness. The first film is exposed to a reactive precursor to form a second film. The second film having a second dielectric constant, a second leakage current, a second breakdown voltage, and a second hardness, wherein the reactive precursor comprises an oxygenated precursor. The second film is exposed to a UV light source to form a third film. The third film having a third dielectric constant, a third leakage current, a third breakdown voltage, and a third hardness.
    Type: Application
    Filed: July 11, 2024
    Publication date: January 15, 2026
    Inventors: Rui LU, Kent Qiujing ZHAO, Bhaskar SOMAN, Bo XIE, Chi-I LANG, Li-Qun XIA, Shankar VENKATARAMAN
  • Publication number: 20250391656
    Abstract: A method for modulating the coefficient of thermal expansion (CTE) of dielectric films on a substrate is provided. In some embodiments, the method includes positioning a substrate within a processing chamber, forming a dielectric film stack on the substrate, and curing the dielectric film with a UV source to modify a CTE of the dielectric film.
    Type: Application
    Filed: June 21, 2024
    Publication date: December 25, 2025
    Inventors: Rui LU, Bo XIE, Chi-I LANG, Li-Qun XIA, Shankar VENKATARAMAN
  • Publication number: 20250385101
    Abstract: Embodiments described herein relate to a method that includes forming a patterning stack over a substrate, wherein the patterning stack includes an underlayer over the substrate that includes an extreme ultraviolet (EUV) sensitive material with —OH terminated chains, and a resist layer over the underlayer. The method further includes exposing regions of the patterning stack with EUV electromagnetic radiation, and increasing a temperature of the patterning stack, wherein OH and/or H2O is released from exposed regions of the underlayer and diffuses into the resist layer. The method may also include developing the resist layer.
    Type: Application
    Filed: May 21, 2025
    Publication date: December 18, 2025
    Inventors: NANCY FUNG, CHI-I LANG, MICHAEL STOLFI, HIDEYUKI KANZAWA, LEQUN LIU
  • Publication number: 20250369102
    Abstract: In some embodiments, a method of forming a dielectric film includes exposing a substrate in a processing chamber to a silicon precursor having general Formula (I) to form a silicon-containing film on the substrate. Formula (I) can be represented by: wherein Q1 is a carbon atom or an oxygen atom, and each of R1, R2, R3, R4, R5, R6, R7, and R8 is independently selected from a hydrogen atom, a substituted alkyl, an unsubstituted alkyl, a substituted alkoxy, an unsubstituted alkoxy, a substituted vinyl, an unsubstituted vinyl, a silane, a substituted amine, an unsubstituted amine, or a halide. The method further includes purging the processing chamber of the silicon precursor.
    Type: Application
    Filed: June 3, 2024
    Publication date: December 4, 2025
    Inventors: Rui LU, Bo XIE, Chi-I LANG, Li-Qun XIA, Shankar VENKATARAMAN
  • Publication number: 20250357107
    Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the nitrogen-containing precursor in the processing region. The plasma may be at least partially formed by an RF power operating at less than or about 1,000 W, at a pulsing frequency less than or about 1,000 Hz, and at a duty cycle between about 10% and 90%. The methods may include forming a layer of material on the substrate. The layer of material may be or include a silicon-and-nitrogen-containing material.
    Type: Application
    Filed: May 16, 2024
    Publication date: November 20, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Kent Zhao, Rui Lu, Xinyi Lu, Bo Xie, Chi-I Lang, Li-Qun Xia, Chidambara A. Ramalingam, Shankar Venkataraman
  • Publication number: 20250313950
    Abstract: Disclosed herewith are a precursor, a gas mixture, and a method for depositing a dielectric film in a processing chamber. A method includes disposing a substrate on a susceptor disposed within a processing chamber; controlling a pressure level and a temperature of the processing chamber; delivering an RF power into the processing chamber; providing a precursor-containing gas mixture into the processing chamber, and applying a post-deposition process to the substrate after the dielectric film is formed on the substrate. The precursor-containing gas mixture includes a precursor and an inert gas selected from the group consisting of argon, nitrogen, and helium. The precursor includes a carbosilane having a Si—C—Si structure in a backbone of the precursor.
    Type: Application
    Filed: April 8, 2025
    Publication date: October 9, 2025
    Inventors: Lakmal C. KALUTARAGE, Lauren Mary BAGBY, Michael HAVERTY, Bo XIE, Chi-I LANG, Bhaskar SOMAN, Rui LU, Kent Qiujing ZHAO, Li-Qun XIA, Shankar VENKATARAMAN
  • Patent number: 12410523
    Abstract: In some embodiments, a method includes positioning a substrate within a processing chamber. The substrate includes a first low-k film having a first water contact angle. The first low-k film is disposed over an interconnect structure. The method further includes cleaning the substrate within the processing chamber to form a cleaned substrate. The cleaned substrate includes a damaged low-k film having a second water contact angle. The method further includes exposing the cleaned substrate to a recovery precursor to form a recovered substrate. The recovered substrate includes a recovered low-k film. The method further includes exposing the recovered substrate to a UV light source to form a treated substrate. The treated substrate includes a treated low-k film having a third water contact angle. The method further includes depositing a liner layer over the treated substrate via atomic layer deposition (ALD).
    Type: Grant
    Filed: July 16, 2024
    Date of Patent: September 9, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Shinjae Kwon, Xinyi Lu, Fredrick Kim, Bo Xie, Chi-I Lang, Li-Qun Xia, Han Wang
  • Publication number: 20250279319
    Abstract: Embodiments of the present disclosure generally relate to layer stacks produced during back-end-of-line (BEOL) process flows. In one or more embodiments, the layer stack is disposed on a substrate and contains a first hard mask layer disposed on a first metal layer, one or more low-k material layers disposed over the first hard mask layer, a second metal layer disposed over the one or more low-k material layers and the first hard mask layer, a second hard mask layer disposed over the second metal layer, and an oxide layer disposed over the second hard mask layer. The second metal layer, the second hard mask layer, and the oxide layer are patterned and form a plurality of features. A gapfill interconnect metal is connected to the first metal layer and the second metal layer and is disposed through the first hard mask layer and the one or more low-k material layers.
    Type: Application
    Filed: May 13, 2025
    Publication date: September 4, 2025
    Inventors: Yung-Chen LIN, Chi-I LANG, Ho-Yung HWANG
  • Publication number: 20250259835
    Abstract: A method for repairing copper and low-k dielectric films on a substrate is provided. In some embodiments, the method includes positioning the substrate within a process chamber, introducing a reducing agent into the process chamber to remove copper oxide from a copper layer on the substrate, removing the reducing agent from the process chamber, and introducing a recovery precursor into the process chamber to decrease a k value of a low-k film on the substrate.
    Type: Application
    Filed: July 25, 2024
    Publication date: August 14, 2025
    Inventors: Xinyi LU, Kent Qiujing ZHAO, Bo XIE, Chi-I LANG, Chengen WANG, Chidambara A. RAMALINGAM, Li-Qun XIA, Shankar VENKATARAMAN
  • Patent number: 12387927
    Abstract: Methods for depositing boron-containing films on a substrate are described. The substrate is exposed to a boron precursor and a plasma to form the boron-containing film (e.g., elemental boron, boron oxide, boron carbide, boron silicide, boron nitride). The exposures can be sequential or simultaneous. The boron-containing films are selectively deposited on one material (e.g., SiN or Si) rather than on another material (e.g., silicon oxide).
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: August 12, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yung-Chen Lin, Chi-I Lang, Ho-yung David Hwang
  • Publication number: 20250253158
    Abstract: Embodiments disclosed herein comprise a method for patterning a stack. In an embodiment, the method comprises providing a substrate with a hardmask layer over the substrate, and depositing an underlayer over the hardmask layer with a dry deposition process, where the underlayer comprises silicon, carbon, oxygen, and hydrogen. In an embodiment, the method further comprises forming a resist layer over the underlayer, exposing and developing the resist layer to form a pattern in the resist layer, and transferring the pattern into the underlayer and the hardmask layer with an etch process.
    Type: Application
    Filed: February 5, 2024
    Publication date: August 7, 2025
    Inventors: HUIXIONG DAI, KHOI PHAN, BO XIE, RUI LU, CHI-I LANG, KENT ZHAO
  • Publication number: 20250226235
    Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.
    Type: Application
    Filed: March 25, 2025
    Publication date: July 10, 2025
    Inventors: Yung-chen LIN, Chi-I LANG, Ho-yung HWANG
  • Patent number: 12327764
    Abstract: Methods for formation of a layer stack during a back-end-of-line (BEOL) process flow and the layer stack formed therefrom are provided. In one or more embodiments, the method utilizes a two-dimensional (2D) self-aligned scheme with a subtractive metal etch. The method includes using a hard mask to form a via with a small width which is formed through or contacts each of a first metal layer and a second metal layer. The via is filled with a metal gapfill to connect the first metal layer and the second metal layer. Each of the first metal layer and the second metal layer are patterned to form a plurality of features.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: June 10, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yung-chen Lin, Chi-I Lang, Ho-yung Hwang