Patents by Inventor Chi-I Lang

Chi-I Lang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7919446
    Abstract: Compositions comprise a purine compound; an alcohol amine; a quaternary ammonium salt; an amino acid, and optionally an antioxidant. The compositions are useful in post-CMP cleaning processes. One particular advantage of these compositions is that they can effectively remove slurry contamination without increasing the roughness of the copper surface.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: April 5, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Zachary M. Fresco, Anh Duong, Chi-I Lang, Nikhil Kalyankar, Nicole Rutherford, Alexander Gorer
  • Patent number: 7915139
    Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: March 29, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
  • Patent number: 7902064
    Abstract: A layer to enhance nucleation of a substrate is described, including a method to form the layer, the method including obtaining a substrate comprising a patterned feature comprising a dielectric region and a conductive region, selectively forming a self-aligned monolayer (SAM) on the dielectric region of the substrate to enhance nucleation process of a first precursor, and depositing the first precursor on the substrate, the precursor to adsorb on the SAM.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: March 8, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Tony Chiang, Chi-I Lang, Zachary Fresco
  • Patent number: 7888233
    Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 15, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
  • Patent number: 7884036
    Abstract: Methods for treating a substrate in preparation for a subsequent process are presented, the method including: receiving the substrate, the substrate comprising conductive regions and dielectric regions; and applying an oxidizing agent to the substrate in a manner so that the dielectric regions are oxidized to become increasingly hydrophilic to enable access to the conductive regions in the subsequent process, wherein the dielectric region is treated to a depth in the range of approximately 1 to 5 atomic layers. In some embodiments, methods further include processing the substrate, wherein processing the conductive regions are selectively enhanced. In some embodiments, the oxidizing agent includes atmospheric pressure plasma and UV radiation.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: February 8, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Jinhong Tong, Anh Duong, Zhi-Wen Sun, Chi-I Lang, Sandra Malhotra, Tony Chiang
  • Patent number: 7879710
    Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 1, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Zachary Fresco, Chi-I Lang, Sandra G. Malhotra, Tony P. Chiang, Thomas R. Boussie, Nitin Kumar, Jinhong Tong, Anh Duong
  • Publication number: 20100203731
    Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Inventors: Bob Kong, Zhi-Wen Sun, Chi-I Lang, Jinhong Tong, Tony Chiang
  • Patent number: 7745328
    Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: June 29, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Melissa M. Tam, Dian Sugiarto, Chi-I Lang, Peter Wai-Man Lee, Li-Qun Xia
  • Patent number: 7727906
    Abstract: This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: June 1, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Sunil Shanker, Chi-I Lang, Minh Anh Nguyen, Judy H. Huang
  • Patent number: 7704789
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: April 27, 2010
    Assignee: Intermolecular, Inc.
    Inventors: Zhi-wen Sun, Nitin Kumar, Jinhong Tong, Chi-I Lang, Tony Chiang
  • Patent number: 7678607
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 16, 2010
    Assignee: Intermolecular, Inc.
    Inventors: Tony Chiang, Chi-I Lang, Zhi-wen Sun, Jinhong Tong, Nitin Kumar
  • Patent number: 7658790
    Abstract: An electroless solution for deposition of a cobalt-based alloy on a substrate is provided. The electroless solution may be formed by mixing first and second solutions, with the first and second solutions being prepared from concentrated precursors. In one embodiment, the first solution contains a cobalt (Co) ion source and a complexing and deposition selectivity agent. In one embodiment, the cobalt concentration in the first solution is at least 90 millimoles per liter. The second solution contains a reducing agent. In one embodiment, the reducing agent is dimethylamineborane (DMAB) having a concentration of at least 10 grams per liter. In other embodiments, the first solution also contains a tungsten (W) ion source, and either the first or second solution also contains a phosphorous (P) ion source.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: February 9, 2010
    Assignee: Intermolecular, Inc.
    Inventors: Alexander Gorer, Tony Chiang, Chi-I Lang
  • Patent number: 7629198
    Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: December 8, 2009
    Assignee: Intermolecular, Inc.
    Inventors: Nitin Kumar, Jinhong Tong, Chi-I Lang, Tony Chiang, Prashant B. Phatak
  • Publication number: 20090291275
    Abstract: Methods for improving selective deposition of a capping layer on a patterned substrate are presented, the method including: receiving the patterned substrate, the patterned substrate including a conductive region and a dielectric region; forming a molecular masking layer (MML) on the dielectric region; preparing an electroless (ELESS) plating bath, where the ELESS plating bath includes: a cobalt (Co) ion source: a complexing agent: a buffer: a tungsten (W) ion source: and a reducing agent; and reacting the patterned substrate with the ELESS plating bath for an ELESS period at an ELESS temperature and an ELESS pH so that the capping layer is selectively formed on the conductive region. In some embodiments, methods further include a pH adjuster for adjusting the ELESS pH to a range of approximately 9.0 pH to 9.2 pH. In some embodiments, the pH adjuster is tetramethylammonium hydroxide (TMAH). In some embodiments, the MML is hydrophilic.
    Type: Application
    Filed: May 22, 2009
    Publication date: November 26, 2009
    Inventors: Jinhong Tong, Zhi-Wen Sun, Chi-I Lang, Nitin Kumar, Bob Kong, Zachary Fresco
  • Publication number: 20090232966
    Abstract: This disclosure provides methods, devices and systems for using a stamp to enhance selectivity between surface layers of a substrate, and to facilitate functionalizing selected layers. An array of flat stamps may be used to concurrently stamp multiple regions of a substrate to transfer one or more substances to the topmost layer or layers of the substrate. If desired, the affected regions of the substrate may be isolated from each other through the use of a reactor plate that, when clamped to the substrate's surface, forms reaction wells in the area of stamping. The stamp area can, if desired, be configured for stamping the substrate after the reactor plate has been fitted, with the individual stamps sized and arranged in a manner that permits stamping within each reaction well.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 17, 2009
    Inventors: Nikhil D. Kalyankar, Zachary Fresco, Chi-I Lang
  • Patent number: 7582555
    Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 1, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
  • Publication number: 20090124081
    Abstract: Techniques to improve characteristics of processed semiconductor substrates are described, including cleaning a substrate using a preclean process, the substrate comprising a dielectric region and a conductive region, introducing a hydroquinone to the substrate after cleaning the substrate using the preclean operation, and forming a capping layer over the conductive region of the substrate after introducing the hydroquinone.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 14, 2009
    Inventors: Anh Ngoc Duong, Chi-I Lang
  • Patent number: 7524735
    Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: April 28, 2009
    Assignee: Novellus Systems, Inc
    Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
  • Patent number: 7514375
    Abstract: During bottom filling of high aspect ratio gaps and trenches in an integrated circuit substrate using HDP-CVD, a pulsed HF bias is applied to the substrate. In some embodiments, pulsed HF bias is applied to the substrate during etching operations. The pulsed bias typically has a pulse frequency in a range of about from 500 Hz to 20 kHz and a duty cycle in a range of about from 0.1 to 0.95.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: April 7, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Sunil Shanker, Chi-I Lang
  • Publication number: 20090075095
    Abstract: Methods for processing a substrate utilizing a backside layer are presented including: receiving a substrate, the substrate including a front side and a backside; forming the backside layer on the backside of the substrate; and performing at least one processing operation on the front side of the substrate, wherein the backside layer protects the backside of the substrate during the performing the at least one processing operation. In some embodiments, methods further include cross-linking the backside layer such that the backside layer is stabilized. In some embodiments, methods further include: functionalizing the backside layer, where the functionalizing alters a chemical characteristic of the backside layer, and where the functionalizing includes a functional group such as: a hydroxyl group, an amino group, a mercapto group, a fluorine group, a chlorine group, an alkene group, an aryle group, and a carboxy group.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 19, 2009
    Inventors: Igor Ivanov, Tony Chiang, Chi-I Lang