Patents by Inventor Chi-Jen Liu

Chi-Jen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12359090
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Chi-Jen Liu, Chih-Chieh Chang, Kao-Feng Liao, Peng-Chung Jangjian, Chun-Wei Hsu, Ting-Hsun Chang, Liang-Guang Chen, Kei-Wei Chen, Hui-Chi Huang
  • Patent number: 12347735
    Abstract: In-situ defect count detection in post chemical mechanical polishing (post-CMP) is provided. Post-CMP is performed, in-situ and according to a recipe, on a surface of a semiconductor wafer within a post-CMP chamber. A light signal is scanned over a target area of the surface of the semiconductor wafer and a reflected light signal reflected from the target area is detected. A defect count of defects present in the target area is determined based on the reflected light signal reflected from the target area.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chun-Hung Liao, Jeng-Chi Lin, Chi-Jen Liu, Liang-Guang Chen, Huang-Lin Chao
  • Patent number: 12297375
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Chi-Jen Liu, Liang-Guang Chen, Kei-Wei Chen, Chun-Wei Hsu, Li-Chieh Wu, Peng-Chung Jangjian, Kao-Feng Liao, Fu-Ming Huang, Wei-Wei Liang, Tang-Kuei Chang, Hui-Chi Huang
  • Patent number: 12224179
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Chi-Hsiang Shen, Te-Ming Kung, Chun-Wei Hsu, Chia-Wei Ho, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20240420978
    Abstract: Provided is a chemical-mechanical polishing apparatus, a retaining ring for a chemical-mechanical polishing apparatus, and a chemical-mechanical polishing method. A chemical-mechanical polishing apparatus includes a polishing pad; a polishing head configured to receive a wafer and to hold the wafer against the polishing pad; and a retaining ring configured to engage with the polishing head, wherein the retaining ring is formed with channels configured for flowing a slurry in a flow direction from outside the retaining ring to inside the retaining ring, wherein the channels have a cross-sectional flow area that decreases in the flow direction.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Chi LIN, Chi-hsiang SHEN, Te-Chien HOU, Tang-Kuei CHANG, Chi-Jen LIU, Hui-Chi HUANG, Kei-Wei CHEN
  • Publication number: 20240379421
    Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Inventors: CHUN-WEI HSU, CHIH-CHIEH CHANG, YI-SHENG LIN, JIAN-CI LIN, JENG-CHI LIN, TING-HSUN CHANG, LIANG-GUANG CHEN, JI CUI, KEI-WEI CHEN, CHI-JEN LIU
  • Patent number: 12131944
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Hsu, Chih-Chieh Chang, Yi-Sheng Lin, Jian-Ci Lin, Jeng-Chi Lin, Ting-Hsun Chang, Liang-Guang Chen, Ji Cui, Kei-Wei Chen, Chi-Jen Liu
  • Publication number: 20240342856
    Abstract: A method of performing a polishing process is provided. The method may include forming spherical titanium dioxide nano-particles, covering the spherical titanium dioxide nano- particles with an organic coating, storing the spherical titanium dioxide nano-particles together with an oxidizer, forming a polishing solution with the spherical titanium dioxide nano-particles, applying the polishing solution on a surface of a work piece, and polishing the surface of the work piece with the polishing solution.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: Sheng-Mu You, Chi-Jen Liu
  • Publication number: 20240290629
    Abstract: A method for CMP includes following operations. A first metal layer and a second metal layer are formed in a dielectric structure. The second metal layer is formed over a portion of the first metal layer. A first composition is provided to remove a portion of the first metal layer. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed to expose the second metal layer. A CMP operation is performed to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure.
    Type: Application
    Filed: April 29, 2024
    Publication date: August 29, 2024
    Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU
  • Patent number: 12002684
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Patent number: 11996283
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
  • Publication number: 20230365903
    Abstract: A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Pinlei Edmund Chu, Chun-Wei Hsu, Ling-Fu Nieh, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Patent number: 11773353
    Abstract: A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pinlei Edmund Chu, Chun-Wei Hsu, Ling-Fu Nieh, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Publication number: 20230298949
    Abstract: In-situ defect count detection in post chemical mechanical polishing (post-CMP) is provided. Post-CMP is performed, in-situ and according to a recipe, on a surface of a semiconductor wafer within a post-CMP chamber. A light signal is scanned over a target area of the surface of the semiconductor wafer and a reflected light signal reflected from the target area is detected. A defect count of defects present in the target area is determined based on the reflected light signal reflected from the target area.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Inventors: Chun-Hung LIAO, Jeng-Chi LIN, Chi-Jen LIU, Liang-Guang CHEN, Huang-Lin CHAO
  • Publication number: 20230294237
    Abstract: A chemical mechanical polishing (CMP) system includes a polishing pad configured to polish a substrate. The CMP system further includes a heating system configured to adjust a temperature of the polishing pad. The heating system comprises at least one heating element spaced apart from the polishing pad. The CMP system further includes a sensor configured to measure the temperature of the polishing pad.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 21, 2023
    Inventors: Yi-Sheng LIN, Chi-Hsiang SHEN, Chi-Jen LIU, Chun-Wei Hsu, Yang-Chun CHENG, Kei-Wei CHEN
  • Publication number: 20230230846
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 20, 2023
    Inventors: Yi-Sheng LIN, Chi-Jen LIU, Chi-Hsiang SHEN, Te-Ming KUNG, Chun-Wei HSU, Chia-Wei HO, Yang-Chun CHENG, William Weilun HONG, Liang-Guang CHEN, Kei-Wei CHEN
  • Patent number: 11658065
    Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Chi-Hsiang Shen, Ting-Hsun Chang, Li-Chieh Wu, Hung Yen, Chi-Jen Liu, Liang-Guang Chen, Kei-Wei Chen
  • Patent number: 11637021
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Chi-Hsiang Shen, Te-Ming Kung, Chun-Wei Hsu, Chia-Wei Ho, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Patent number: 11633829
    Abstract: A chemical mechanical polishing (CMP) system includes a polishing pad configured to polish a substrate. The CMP system further includes a heating system configured to adjust a temperature of the polishing pad. The heating system comprises at least one heating element spaced apart from the polishing pad. The CMP system further includes a sensor configured to measure the temperature of the polishing pad.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Sheng Lin, Chi-Hsiang Shen, Chi-Jen Liu, Chun-Wei Hsu, Yang-Chun Cheng, Kei-Wei Chen
  • Publication number: 20230082084
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU