Patents by Inventor Chi Lin

Chi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250226322
    Abstract: The present disclosure is directed to a structure of an interconnect layer and a method of forming the structure. The interconnect layer includes first and second regions. The first region includes a first dielectric layer and a first interconnect structure. The second region includes a second dielectric layer and a second interconnect structure. The first region has a first ratio of a metal surface area to a non-metal surface area in the first region. The second region has a second ratio of a metal surface area to a non-metal surface area in the second region. The first and second ratios are different. The first and second dielectric layers include dielectric materials selected and/or treated differently according to the first and second ratios to substantially match polishing rates of the first and second regions in a planarization process.
    Type: Application
    Filed: January 5, 2024
    Publication date: July 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ren Sun, Kun-Ei Chen, Chun-Jen Chen, Sheng-Tang Wang, Shih-Chi Lin, Kai-Shiung Hsu, Kang-Min Kuo, Su-Yu Yeh
  • Publication number: 20250213106
    Abstract: An oral scanner system having an oral scanner, the oral scanner having a handle, a head, a camera, a spacer attachment being detachably attached to the head, and a processor being arranged to receive at least one signal from the camera to determine, based on an analysis of the at least one signal, an attachment state of the spacer attachment.
    Type: Application
    Filed: December 19, 2024
    Publication date: July 3, 2025
    Inventors: Reiner ENGELMOHR, Rüdiger BOSS, Devran ALBAY, Dominik Heinz LANGHAMMER, Ingo VETTER, Kai-Ju CHENG, Hsin-Lun HSIEH, Chin-Yuan TING, Tsung-Hsin LU, Chin-Kang CHANG, Chao-Ching HUANG, Wan-Chi LIN, Tao-Feng CHEN
  • Patent number: 12348054
    Abstract: A wireless power transmitter circuit includes: a power stage circuit including plural switches coupled to a resonant transmitter circuit, wherein the resonant transmitter circuit includes a transmission coil and a resonant capacitor which are coupled to each other; and a transmission control circuit controlling the power stage circuit to convert an input power to a driving power according to a pulse width modulation (PWM) control signal when a corresponding wireless power receiver circuit is near by the resonant transmitter circuit. The driving power drives the resonant transmitter circuit to generate a wireless transmitting power, which is supplied to the corresponding wireless power receiver circuit. When a variation rate of a driving current of the driving power with respect to time exceeds a variation rate threshold, an operation parameter of the power stage circuit is adjusted to reduce a power level of the wireless transmitting power.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: July 1, 2025
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Fu-Chi Lin
  • Publication number: 20250194750
    Abstract: An adjustment system for an article of footwear includes a body attached to an outer surface of the article of footwear and including a plurality of segments cooperating to define a chamber, the body movable between an elongated state and a collapsed state and a bladder attached to the article of footwear and defining an interior void in fluid communication with the chamber, the bladder movable from a relaxed state to a constricted state when the body is moved from the collapsed state to the elongated state.
    Type: Application
    Filed: December 16, 2024
    Publication date: June 19, 2025
    Applicant: NIKE, Inc.
    Inventors: Austin J. Orand, Yen-Lin Lee, To-Chun Lin, Chih-Ta Chien, Richard Kristian Hansen, Chia-Chi Lin, Kimberly A. Sokol
  • Patent number: 12330152
    Abstract: A microfluidic sensor chip includes a body comprising a substrate and an upper cover, and the upper cover having at least one opening, at least one microfluidic channel formed on the substrate and has a supporting surface, wherein the at least one microfluidic channel communicates with the at least one opening, and a metamaterial layer coated on the supporting surface, wherein the metamaterial layer has a plurality of regions, and each region has a corresponding resonance pattern. The present disclosure further provides a measuring system for microfluidic sensor chip includes a carrying board, a plurality of the microfluidic sensor chips, a transmitter emitting a terahertz wave corresponding to the resonance pattern of one of the microfluidic sensor chips, a receiver receiving a reflected wave corresponding to the terahertz wave, and a processor receiving the reflected wave from the processor, and determining a testing sample characteristic according to the reflected wave.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: June 17, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Tai Li, Chia-Jen Lin, Wei-Yu Lin, Kao-Chi Lin, Cho-Fan Hsieh, Teng-Chun Wu
  • Publication number: 20250192758
    Abstract: A data retention circuit includes a flip-flop circuit including a master latch coupled to a slave latch, wherein the slave latch includes a first input terminal and a first output terminal, and a series combination of a retention latch and a level shifter coupled between the first input terminal and the first output terminal. The slave latch is configured to be selectively coupled to the series combination through a first transmission gate responsive to a restore signal.
    Type: Application
    Filed: February 20, 2025
    Publication date: June 12, 2025
    Inventors: Kai-Chi HUANG, Yung-Chen CHIEN, Chi-Lin LIU, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
  • Publication number: 20250183387
    Abstract: An automatic pressure adjustment device for measuring the pressurization demand of battery cells includes a linear force output module, a pressing module, and an elastic module. The pressing module includes a pressing plate and a guide rail. The guide rail is parallel to the linear force direction. The pressing plate is moved along the guide rail by the linear force of the linear force output module. The elastic module includes a first plate, a second plate, at least one elastic member, and at least one pressure sensing unit. The first plate and the pressing plate are sandwiched to form a loading space. The plurality of elastic members are disposed between the first plate and the second plate. The compression direction of the plurality of elastic members is along the linear force direction, and the at least one pressure sensing unit is disposed on one side of the second plate.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 5, 2025
    Inventors: FU-MIN FANG, CHI-LIN WU, CHIH-HSIEN CHUNG, SHIH-CHANG TSENG, GWO-HUEI YOU, KUO-KUANG JEN
  • Publication number: 20250174037
    Abstract: An apparatus may include an ultrasonic sensor stack, a foldable display stack and a transmission enhancement layer. The foldable display stack may include a display stiffener and display stack layers. The display stack layers may form one or more display stack resonators configured to enhance ultrasonic waves transmitted by the ultrasonic sensor stack in a first ultrasonic frequency range. In some implementations, a transmission enhancement resonator may include the display stiffener and the transmission enhancement layer. In some examples, the transmission enhancement resonator may include at least a portion of the ultrasonic sensor stack. The transmission enhancement resonator may be configured to enhance the ultrasonic waves transmitted by the ultrasonic sensor stack in the first ultrasonic frequency range.
    Type: Application
    Filed: January 23, 2025
    Publication date: May 29, 2025
    Inventors: Shiang-Chi LIN, Hrishikesh Vijaykumar PANCHAWAGH, Jessica Liu STROHMANN, Yipeng LU, Chin-Jen TSENG, Kostadin Dimitrov DJORDJEV, Min-Lun YANG, Chia-Wei YANG
  • Publication number: 20250167042
    Abstract: A method for manufacturing a semiconductor device includes: forming a conductive structure; forming an interconnect layer on the conductive structure, the interconnect layer including a conductive interconnect that is electrically connected to the conductive structure; and forming multiple conductive features and multiple spacer features on the interconnect layer, adjacent two of the conductive features being spaced apart from each other by a corresponding one of the spacer features, one of the conductive features being electrically connected to the conductive interconnect, each of the spacer features including a dielectric spacer layer contacting lateral surfaces of two of the conductive features that are adjacent to the spacer feature, and a cover segment disposed on the dielectric spacer layer and cooperating with the dielectric spacer layer to define an air gap between the two of the conductive features that are adjacent to the spacer feature.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 22, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Ya LO, Gary LIU, Chi-Lin TENG, Zi-Yi YANG, Chuan-Pu CHOU, Hsin-Yen HUANG, Chia-Tien WU, Hsiao-Kang CHANG, Shao-Kuan LEE, Chia-Chen LEE
  • Publication number: 20250161633
    Abstract: A detachable urethral catheterization device for guiding a movement of a urinary catheter is provided. The detachable urethral catheterization device includes a conveying body and a clamping module. The conveying body includes a driving module, a conveying channel, and a module accommodating groove in communication with the conveying channel, the module accommodating groove including a first coupling component. The clamping module coupled to the driving module, and having a second coupling component, where the second coupling component is detachably coupled to the first coupling component in the module accommodating groove, and where the driving module is configured to control the clamping module to clamp the urinary catheter and move the urinary catheter in the conveying channel and the module accommodating groove.
    Type: Application
    Filed: December 1, 2023
    Publication date: May 22, 2025
    Inventors: MING-CHIEN CHIU, Yung-Chin Pan, Chia-Ch Lin, Chi-Lin Li, Meng-Hsuan Liu
  • Publication number: 20250154060
    Abstract: Methods for asphalt paving disclosed here incorporate waste recycled asphalt shingles (RAS) or polyethylene (PE) plastics, resulting in durable paving, resistant to rutting and cracking. Methods include mixing RAS or PE as an additive to a designed mix containing loose aggregate and a virgin binder such as asphalt or tar and compacting the mix onto a paving substrate.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 15, 2025
    Inventors: Haifang Wen, Maziar Mivehchi, Chi-Lin Chiang
  • Publication number: 20250158005
    Abstract: A wafer on wafer on wafer and a chip on wafer on wafer structure and methods of forming the same are provided. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding and additional device wafers may subsequently be bonded to the first device wafer. A support wafer is then bonded to the top most device wafer and the first wafer may then be removed. The bonded wafer structure may then be singulated into individual semiconductor device packages. Through the wafer-on-wafer bonding process, the manufacturing cost and cycle time may be reduced.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 15, 2025
    Inventors: Yen-Ming Chen, Yung-Chi Lin
  • Patent number: 12301228
    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
    Type: Grant
    Filed: April 24, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Greg Gruber, Chi-Lin Liu, Ming-Chang Kuo, Lee-Chung Lu, Shang-Chih Hsieh
  • Publication number: 20250149497
    Abstract: A bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. The hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh
  • Publication number: 20250149436
    Abstract: A method for manufacturing an interconnect structure includes: forming sacrificial portions and electrically conductive portions on a base structure such that the sacrificial portions are disposed to alternate with the electrically conductive portions in a first direction, and such that each of the sacrificial portions and the electrically conductive portions is elongated in a second direction transverse to the first direction; forming blocking portions respectively on the sacrificial portions; forming a sacrificial layer to cover the electrically conductive portions and the blocking portions; forming an electrically conductive via which extends through the sacrificial layer so as to permit the electrically conductive via to be electrically connected to one of the electrically conductive portions; after forming the electrically conductive via, performing a removal process to remove the sacrificial layer, the blocking portions and the sacrificial portions so as to form a cavity; and forming a dielectric portio
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gary LIU, Ting-Ya LO, Shao-Kuan LEE, Zi-Yi YANG, Chi-Lin TENG, Kuang-Wei YANG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Ming-Han LEE, Shau-Lin SHUE
  • Publication number: 20250132247
    Abstract: An interconnection structure is provided to include a substrate, a first metal trench, a boron nitride dielectric, a second metal trench, and a metal via. The substrate is formed with a first metal trench. The boron nitride dielectric is disposed over the substrate. The second metal trench is formed in the boron nitride dielectric. The metal via is disposed to interconnect the first metal trench and the second metal trench.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin TENG, Gary LIU, Ting-Ya LO, Yen-Ju WU, Shao-Kuan LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Hsiao-Kang CHANG
  • Publication number: 20250132197
    Abstract: A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, an etch stop layer formed of a metal oxide composite and disposed on a top surface of the substrate, and a second conductive feature disposed on and through the etch stop layer and in contact with the first conductive feature. The metal oxide composite contains a metal element represented by M, and a top surface of the etch stop layer includes an M—O—X group, O representing oxygen, and X representing an element other than hydrogen.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 24, 2025
    Inventors: Kai-Feng Cheng, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang
  • Patent number: 12283512
    Abstract: A method includes: positioning a wafer on an electrostatic chuck of an apparatus; and securing the wafer to the electrostatic chuck by: securing a first wafer region of the wafer to a first chuck region of the electrostatic chuck by applying a first voltage at a first time. The method further includes securing a second wafer region of the wafer to a second chuck region of the electrostatic chuck by applying a second voltage at a second time different from the first time; and processing the wafer by the apparatus while the wafer is secured to the electrostatic chuck.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuang-Shiuan Deng, Fan-Chi Lin, Chueh-Chi Kuo, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20250125515
    Abstract: A mobile device supporting wideband operations includes a first metal mechanism element, a dielectric substrate, a first feeding radiation element, a second feeding radiation element, a ground element, and a second metal mechanism element. The first metal mechanism element includes a main portion and a sidewall portion. The sidewall portion of the first metal mechanism element has a first slot. Both the first feeding radiation element and the second feeding radiation element extend across the first slot of the first metal mechanism element. An antenna structure is formed by the first slot of the first metal mechanism element, the dielectric substrate, the first feeding radiation element, the second feeding radiation element, and the ground element. The second metal mechanism element is disposed opposite to the main portion of the first metal mechanism element. The second metal mechanism element has a second slot.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 17, 2025
    Inventors: Kun-Sheng CHANG, Ching-Chi LIN, Chuan-Chun WANG
  • Patent number: D1078595
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: June 10, 2025
    Inventors: Min Chi Lin, Yu Hao Hsu, Chen Yang Yu, Jyun Yi Ke, Yu Chia Hsieh