Patents by Inventor Chi Lin

Chi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966133
    Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: April 23, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
  • Patent number: 11967112
    Abstract: Described is a method for detecting a calibration requirement for image sensors in a vehicle. The method includes detecting a ground pattern in a generated image associated with a surrounding of a vehicle. The method includes extracting at least one key point associated with the detected ground pattern, from the generated image. The method includes determining a relative motion parameter associated with the extracted at least one key point based on tracking of the extracted at least one key point over a period of time. The method further includes detecting the calibration requirement for the image sensor based on the determined relative motion parameter and generating an output signal based on the detected calibration requirement.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: April 23, 2024
    Assignee: AitronX Inc.
    Inventors: Xinlu Tang, Chi Yan, Jiangwei Li, Jie Lin
  • Publication number: 20240123559
    Abstract: A fixation device is adapted to be mounted with a machine tool and mounted to a machine bed. The fixation device includes a fixed seat, a magnetic unit, and at least one ejection unit. The fixed seat has a bottom surface and a plurality of grooves formed in the bottom surface. The magnetic unit includes a plurality of magnet blocks fixed respectively in the grooves and adapted to be magnetically positioned on the machine bed. The at least one ejection unit is mounted on the fixed seat, and includes an operating member and a supporting member. The operating member is operable to move the supporting member from a first position, where a bottom end of the supporting member is flush with the bottom surface of the fixed seat, to a second position, where the bottom end of the supporting member protrudes out from the bottom surface of the fixed seat.
    Type: Application
    Filed: December 28, 2022
    Publication date: April 18, 2024
    Inventor: Ching-Chi LIN
  • Publication number: 20240126559
    Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.
    Type: Application
    Filed: March 15, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chi HUANG, Shu-Cheng CHOU, Yu-Hsiang LIN
  • Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Patent number: 11961745
    Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Yu Lin, Shih-Chi Kuo, Chun-Chieh Mo
  • Publication number: 20240120304
    Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.
    Type: Application
    Filed: November 24, 2022
    Publication date: April 11, 2024
    Applicant: Innolux Corporation
    Inventors: Tzu-Sheng Wu, Haw-Kuen Liu, Chung-Jyh Lin, Cheng-Chi Wang, Wen-Hsiang Liao, Te-Hsun Lin
  • Publication number: 20240120300
    Abstract: A chip package which includes a glass fiber substrate made of FR-4 fiberglass is provided. The chip package further includes a substrate pad which is a stacked metal structure with a certain thickness and composed of a nickel layer, a palladium layer, and a gold layer, or a nickel layer and a gold layer stacked over at least one first circuit layer in turn. A total thickness of the substrate pad is 3.15-5.4 ?m. The glass fiber substrate and the substrate pad can bear positive pressure generated during wire bonding. Thereby at least one solder joint is formed on the substrate pad precisely and integrally. This helps reduction in material cost for manufacturers.
    Type: Application
    Filed: September 8, 2023
    Publication date: April 11, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Patent number: 11951901
    Abstract: A display system suitable for a vehicle is provided. The display system suitable for the vehicle includes a center console, a processing device, and a display device. The center console is configured to generate a power sequence according to a customization setting, and the power sequence corresponds to content of a data table. The processing device is configured to receive the power sequence and decodes the power sequence through a lookup table to generate a decoding result. The lookup table includes the content of the data table. The display device is coupled to the processing device and is configured to display a display image according to the decoding result.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: April 9, 2024
    Assignee: Coretronic Corporation
    Inventors: Jui-Ta Liu, Wen-Chang Chien, Tsung-Hsin Yeh, Shao-Chi Lin
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11955541
    Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee
  • Patent number: 11952690
    Abstract: A breathable and waterproof non-woven fabric is manufactured by a manufacturing method including the following steps. Performing a kneading process on 87 to 91 parts by weight of a polyester, 5 to 7 parts by weight of a water repellent, and 3 to 6 parts by weight of a flow promoter to form a mixture, in which the polyester has a melt index between 350 g/10 min and 1310 g/10 min at a temperature of 270° C., and the mixture has a melt index between 530 g/10 min and 1540 g/10 min at a temperature of 270° C. Performing a melt-blowing process on the mixture, such that the flow promoter is volatilized and a melt-blown fiber is formed, in which the melt-blown fiber has a fiber body and the water repellent disposed on the fiber body with a particle size (D90) between 350 nm and 450 nm.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN TEXTILE RESEARCH INSTITUTE
    Inventors: Ying-Chi Lin, Wei-Hung Chen, Li-Chen Chu, Rih-Sheng Chiang
  • Patent number: 11953459
    Abstract: A multi-functional sensor assembly includes an electrically non-conductive substrate defining at least a distal region, intermediary region, and proximal region that are each covered with electrically conductive traces. The proximal region is configured to be exposed to a media to be sensed and the distal and intermediary regions are configured to be protected from the media. The electrically conductive traces comprise at least electrical circuits to sense temperature and flow of the media and one or more electrodes to sense one or more of conductivity, oxidation reduction potential (ORP), and acidity (pH) of the media.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: April 9, 2024
    Assignees: MASCO CORPORATION, The Regents of the University of Michigan
    Inventors: Klaus Brondum, Mark Andrew Burns, Wen-Chi Lin, Michael McCague, Stephen Michael Stec, Brian N. Johnson, Garry Marty
  • Publication number: 20240112688
    Abstract: The present disclosure provides an audio compression device, an audio compressing system and an audio compression method. The audio compression device comprises a first transceiver and a first processor. The first transceiver is connected to the first processor. The processor obtains an audio signal and an available bandwidth, and the processor performs an audio compression encoding on the audio signal to obtain a sample audio signal, and then compares with the audio signal and the sample audio signal to generate a residual signal, and the residual signal is transmitted according to the available bandwidth. The audio signal can be completely transmitted to an audio decompression device to reduce the distortion of the audio signal.
    Type: Application
    Filed: October 4, 2022
    Publication date: April 4, 2024
    Applicant: SAVITECH CORP.
    Inventors: Sing-Ban Robert TIEN, Wen-Wei KANG, Wu-Lin CHANG, Chi-Feng HUANG, Lee-Chang PANG
  • Publication number: 20240108592
    Abstract: Provided is a method for treating cancer by administering to a subject in need thereof with a pharmaceutical composition including a benzenesulfonamide derivative in combination with a cancer immunotherapeutic agent such as the immune check point inhibitor (ICI).
    Type: Application
    Filed: September 19, 2023
    Publication date: April 4, 2024
    Applicant: Gongwin Biopharm Co., Ltd
    Inventors: Shun-Chi WU, Chuan-Ching YANG, Zong-Yu YANG, Chia-En LIN, Mao-Yuan LIN
  • Publication number: 20240112731
    Abstract: Techniques and mechanisms for operating a ferroelectric (FE) circuit element as a cell of a crossbar memory array. In an embodiment, the crossbar memory array comprises a bit line, a word line, and a data storage cell which includes a circuit element that extends to each of the bit line and the word line. The data storage cell is a FE circuit element which comprises terminals, each at a different respective one of the bit line or the word line, and one or more material layers between said terminals. One such layer comprises a FE nitride or a FE oxide. The FE circuit element is operable to selectively enable, or disable, operation as a diode. In another embodiment, the memory array is coupled to circuitry which corresponds a given mode of operation of the FE circuit element to a particular data bit value.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Saima Siddiqui, Sarah Atanasov, Bernal Granados Alpizar, Uygar Avci
  • Publication number: 20240112730
    Abstract: Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Nazila Haratipour, Saima Siddiqui, Uygar Avci, Chia-Ching Lin
  • Patent number: 11946591
    Abstract: A foldable stand has a base, a riser, and a switching mechanism. The riser is located on the base. The switching mechanism connects the base and the riser such that the riser selectively pivots relative to the base from an upright position to a folded position. The switching mechanism has a locked status and a released status. In the locked status, the switching mechanism prevents the riser from pivoting relative to the base. In the released status, the switching mechanism allows the riser to pivot relative to the base from an upright position to a folded position. The switching mechanism is configured to be switched from the locked status to the released status by rotation of the riser around a centerline of the riser.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 2, 2024
    Assignee: Reliance International Corp.
    Inventors: Chi-Chia Huang, Cheng-Lin Ho, Eric Langenhahn
  • Patent number: 11946593
    Abstract: Provided is a grease injection system including a plurality of grease injection devices and a host. The grease injection devices uses control information to output lubricating grease, and output a plurality of pieces of status information. The host receives the pieces of status information from the grease injection devices, and generates the control information based on the pieces of status information.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: April 2, 2024
    Assignee: DORCAS SHIN CO., LTD
    Inventors: Ming-Tan Hsu, Xin-Xin Lin, Li-Hsiang Sun, Wen-Chi Hsieh
  • Patent number: 11948920
    Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou