Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: A method for manufacturing a bump of wafer level package is provided. First, a wafer with multiple pads and a passivation layer exposing the pads is provided, wherein the passivation layer between the pads has scribe lines for dividing chips after the package process. Next, a conducting layer is formed on the wafer, wherein the conducting layer is electrically connected to the pads and filled into the scribe line. Later, a photoresist layer is formed on the conducting layer. The photoresist layer is then patterned to form an opening exposing the conducting layer above the pads and to form at least one opening in the region outside the pads without exposing the conducting layer. Finally, a bump is formed in the opening above the pads to connect with the conducting layer.

Abstract: A method of forming a plurality of bumps over a wafer mainly comprises providing the wafer having a plurality of bonding pads formed thereon, forming an under bump metallurgy (UBM) layer over the bonding pads wherein the UBM layer includes an adhesive layer, for example a titanium (Ti) layer or an aluminum (Al) layer, and at least one electrically conductive layer formed on the adhesive layer, removing the portions of the electrically conductive layer located outside the bonding pads, forming a plurality of bumps over the residual portions of the electrically conductive layer disposed above the bonding pads, etching the adhesive layer located outside the bumps, and then reflowing the bumps.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: The present invention relates to a method for mounting bumps on an under bump metallurgy layer (UBM layer).

Abstract: The present invention relates to a structure of bumps forming on an under bump metallurgy layer (UBM layer) and a method for making the same. The structure comprises a wafer, a UBM layer, a second photo resist and a bump. The wafer has a plurality of solder pads and a protection layer, and the protection layer covers the surface of the wafer and exposes parts of the solder pads. The UBM layer is disposed on the solder pads and the protection layer and has an undercut structure. The second photo resist is disposed in the undercut structure. The bump is disposed on the UMB layer. Whereby, the UMB layer will not be reacted with bump in a reflow process and the problem of stress concentration will be avoided so as to make the bump more stable.

Abstract: A method for forming bumps is disclosed. First, a substrate having an adhesive, a barrier, and a wetting layer thereon is provided. Next, a patterned photoresist is formed on the wetting layer, in which the patterned photoresist includes at least one opening for exposing a portion of the wetting layer. Next, a solder is deposited in the opening, and a stripping process is performed to remove the patterned photoresist. Next, a first etchant is utilized to perform a first etching process for etching a portion of the wetting and barrier layers by utilizing the solder as a mask, in which the first etchant is selected from the group consisting of: sulfuric acid, phosphoric acid, ferric chloride, ammonium persulfate, and potassium monopersulfate. Next, a second etchant is utilized to perform a second etching process removing a portion of the adhesive layer, and a reflow process is performed to form a bump.

Abstract: A method of forming bump protective collars is disclosed. A wafer has an active surface with a plurality of bonding pads and a passivation layer. A plurality of reflowed bumps are formed over the bonding pads. A photoresist is coated on the active surface. Using the reflowed bumps as a photo mask, the photoresist is exposed and developed. After removing the photoresist, a plurality of bump protective collars are formed on the passivation layer and around the reflowed bumps for improving the reliability of the reflowed bumps.

Abstract: A method of forming bump protective collars is disclosed. A wafer has an active surface with a plurality of bonding pads and a passivation layer. A plurality of reflowed bumps are formed over the bonding pads. A photoresist is coated on the active surface. Using the reflowed bumps as a photo mask, the photoresist is exposed and developed. After removing the photoresist, a plurality of bump protective collars are formed on the passivation layer and around the reflowed bumps for improving the reliability of the reflowed bumps.

Abstract: The present invention provides a method for treating the wafer surface, suitable for removing residues on the wafer surface. The method includes forming a photo-sensitive material layer over the wafer surface covering the bumps and the under bump metallurgy layer on the wafer surface. Using the bumps as masks, the photo-sensitive material layer is exposed and developed, to expose the wafer surface between the bumps. A wet etching process is then performed to remove residues on the exposed wafer surface and then the remained photo-sensitive material layer is removed. Therefore, no residues remain on the wafer surface, and the yield of the bumps is increased.

Abstract: A method for forming conductive bumps is applied to a wafer. An under-bump-metallurgy structure and a first photo resist layer are subsequently formed on the wafer. The first photo resist layer, such as a dry film, is patterned to have some openings and then a second photo resist layer is filled into the openings, in which the thickness of the second photo resist layer is fewer than or equal to the thickness of the first photo resist layer. The second photo resist layer is then patterned to have some openings. Next, a conductive layer is formed in the openings and then both the first and second photo resist layers are removed. With the conductive layer as a mask, the exposed under-bump-metallurgy structure is removed and then the conductive layer is reflowed to form some conductive bumps. With two kinds of photo resist layers, the conductive bumps can be provided with increased heights and decreased pitches.

Abstract: A wafer fabricating method at least includes the steps of providing a wafer having an active surface with a plurality of pads, forming a plurality of bumps on the pad, and forming an organic protective layer on the bump and the active surface. Besides improving the quality of the wafer, the wafer structure according to the invention is oxidation-resistant, thus avoiding the cold-joint problem when soldered to the substrate.

Abstract: A method for making UBM (Under Bump Metallurgy) pads and bumps on a wafer is disclosed. Openings are formed in a photoresist layer for forming bumps, a positive liquid photoresist is provided into the openings of the photoresist layer for forming bumps. The positive liquid photoresist is exposed and developed to modify the openings of the photoresist layer. Thus, bumps formed in the modified openings have precise bonding areas on the UBM layer. Using the bumps as a mask, UBM pads under the bumps are formed by etching the UBM layer, so that the reflowed bumps have a uniform height.

Abstract: A catheter balloon formed of a polymeric material such as expanded polytetrafluoroethylene (ePTFE) bonded to a second layer formed of a low tensile set polymer and/or impregnated with a low tensile set polymer. In a presently preferred embodiment, the low tensile set polymer is an elastomer selected from the group consisting of a silicone-polyurethane copolymer and a diene polymer. The low tensile set polymer has high strength, low modulus, high elongation, and low tensile set, to provide improved balloon performance. The diene or silicone-polyurethane has a low tensile set, which facilitates deflation of the balloon to a low profile deflated configuration. One aspect of the invention provides improved attachment of the diene to the ePTFE. In one embodiment, the second layer is formed of a diene mixed with a bonding promoter such as a vulcanizing agent which is covalently bonded to the diene.

Abstract: A method for forming conductive bumps is applied to a wafer. An under-bump-metallurgy structure and a first photo resist layer are subsequently formed on the wafer. The first photo resist layer, such as a dry film, is patterned to have some openings and then a second photo resist layer is filled into the openings, in which the thickness of the second photo resist layer is fewer than or equal to the thickness of the first photo resist layer. The second photo resist layer is then patterned to have some openings. Next, a conductive layer is formed in the openings and then both the first and second photo resist layers are removed. With the conductive layer as a mask, the exposed under-bump-metallurgy structure is removed and then the conductive layer is reflowed to form some conductive bumps. With two kinds of photo resist layers, the conductive bumps can be provided with increased heights and decreased pitches.

Abstract: A wafer bumping process is disclosed. A wafer having a plurality of bonding pads formed thereon is provided. A first under bump metallurgy layer is formed to cover the bonding pads. A first patterned photoresist layer having a plurality of first openings is formed on the first under bump metallurgy layer, wherein a portion of the first under bump metallurgy layer is exposed within the first openings. A second under bump metallurgy layer is formed within the first openings, wherein the second under bump metallurgy layer is much thicker than the first under bump metallurgy layer. A second patterned photoresist layer having a plurality of second openings is formed on the first patterned photoresist layer, wherein the second openings being larger than the first openings.

Abstract: An IC chip with a plurality of improved pillar bumps is disclosed. A chip has a plurality of bonding pads on its active surface. An Under Bump Metallurgy layer (UBM) is formed onto the bonding pads. A solder layer is formed over the UBM layer to connect the pillar bumps so that the pillar bumps will not contact the UBM layer. The solder layer has a melting point lower than that of the pillar bumps. The solder layer can connect the bottom surfaces of the pillar bumps through a reflowing process under shape retaining of the pillar bumps for improving the stress resistance and the bonding strength of the pillar bumps.

Abstract: A bump fabrication process is provided. A substrate having a plurality of openings of various widths thereon is provided. The substrate is dipped into an electrolytic solution. A step current that increases gradually is provided to the solution to perform an electroplating operation so that the conductive material is deposited inside the openings to form bumps with uniform thickness.

Abstract: A method of forming bump protective collars is disclosed. A wafer has an active surface with a plurality of bonding pads and a passivation layer. A plurality of reflowed bumps are formed over the bonding pads. A photoresist is coated on the active surface. Using the reflowed bumps as a photo mask, the photoresist is exposed and developed. After removing the photoresist, a plurality of bump protective collars are formed on the passivation layer and around the reflowed bumps for improving the reliability of the reflowed bumps.

Abstract: A packaging fabrication for an organic electroluminescence panel is disclosed. The panel comprises a printed circuit board, one or a plurality of OEL panels and a plurality of bumps, wherein the OEL is provided with poly solder interconnections in area array. The printed circuit board is provided with a plurality of solder pads arranged with bumps. One or a plurality of OEL is arranged on the printed circuit board and the poly solder interconnections and bumps are used to electrically connect the OEL with the printed circuit board. Further, the excellent heat dissipation property of the low re-flow temperature of the poly solder interconnections and the ceramic printed circuit board provides packaging fabrication for low temperature low stress OEL.