Abstract: A rekeyable lock includes a lock casing formed with a lock cylinder hole, a pin replacing hole and a plurality of first pin holes; a lock cylinder rotatably arranged in the lock cylinder hole and formed with a plurality of second pin holes; a pin set including a plurality of first pins respectively accommodated in the first pin holes, and a plurality of second pins respectively accommodated in the second pin holes; and a pin cover arranged in the pin replacing hole and including a cover body formed with a groove, and a sliding block arranged in the groove and slidable relative to the cover body. When the sliding block is located at a predetermined position, the sliding block and the cover body are configured to respectively abut against an inner wall of the lock casing to fix the pin cover in the pin replacing hole.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: An electric lock has a lock cylinder operable with a key. The lock cylinder has a latch drive lever extending along an axis. A clutch mechanism of the electric lock includes a fixed base fixedly connected to the lock cylinder, a rotatable knob rotatable on the fixed base, a clutch part movable along the axis and rotatable about the axis on the fixed base, a linkage part rotatable about the axis on the fixed base, and a driving device. The clutch part can drive the latch drive lever to rotate. The linkage part and the clutch part are against each other along the axis. The driving device is coupled with the linkage part so as to drive the linkage part to rotate about the axis, so that the clutch part is moved along the axis to be engaged with or disengaged from the rotatable knob.

Abstract: Scribe line channels are formed between semiconductor dies that are formed on a gallium nitride (GaN) layer using an aluminum nitride-based (AlN-based) core substrate. The scribe line channels are formed to expose a release layer under the GaN layer, which enables the release layer to be etched through the scribe line channels to remove the semiconductor dies from the AlN-based core substrate with minimal to no damage to the AlN-based core substrate. In this way, the scribe line channels enable the AlN-based core substrate to be reused for subsequent GaN layer growth, and increase the number of times that the AlN-based core substrate can be reused to form GaN-based semiconductor devices. This reduces the cost and complexity of manufacturing GaN-based semiconductor devices.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a semiconductor substrate including a first region and a second region surrounding the first region, a III-V semiconductor layer disposed directly over the first region, a compound semiconductor device formed in and over the III-V semiconductor layer, a first plurality of conductive features disposed over and electrically coupled to a source contact of the compound semiconductor device, and a seal ring disposed directly over the second region and comprising a second plurality of conductive features, a top surface of a topmost conductive feature of the first plurality of conductive features is higher than a top surface of a topmost conductive feature of the second plurality of conductive features.

Abstract: A lockset includes a lock cylinder, a lock casing, a first lock member, a second lock member and an anti-theft member. The lock cylinder includes a key hole and a first lock slot. The lock casing includes a second lock slot. The first lock member is accommodated in the first lock slot. The second lock member is accommodated in the second lock slot. The anti-theft member is sandwiched in between the first lock member and the second lock member. When two ends of the anti-theft member are respectively located in the first lock slot and the second lock slot, the lock cylinder and the lock casing are locked. When a contact surface between the anti-theft member and the first lock member or the second lock member is aligned with a rotation interface between the lock cylinder and the lock casing, the lock cylinder and the lock casing are unlocked.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first transistor on a semiconductor substrate. The first transistor includes a first gate structure over the semiconductor substrate, a first pair of source/drain regions on opposing sides of the first gate structure, and a pair of diffusion barrier structures between the first pair of source/drain regions and a lower region of the semiconductor substrate. The first pair of source/drain regions comprise a first dopant. The diffusion barrier structures are co-doped with the first dopant and a second dopant different from the first dopant. A doping concentration of the first dopant within the first pair of source/drain regions is greater than a doping concentration of the first dopant within the diffusion barrier structures.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a semiconductor substrate including a first region and a second region surrounding the first region, a III-V semiconductor layer disposed directly over the first region, a compound semiconductor device formed in and over the III-V semiconductor layer, a first plurality of conductive features disposed over and electrically coupled to a source contact of the compound semiconductor device, and a seal ring disposed directly over the second region and comprising a second plurality of conductive features, a top surface of a topmost conductive feature of the first plurality of conductive features is higher than a top surface of a topmost conductive feature of the second plurality of conductive features.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: A lock core device includes a receiving sleeve and a lock cylinder rotatable relative to the receiving sleeve. The lock cylinder is formed with a keyway to selectively receive a first type key with a first section contour or a second type key with a second section contour different from the first section contour. A first side of the keyway is formed with a first abutting structure to allow the first type key to abut against in order to position a bottom of the first type key relative to the keyway along a height direction of the keyway. A second side of the keyway is formed with a second abutting structure to allow the second type key to abut against in order to position a bottom of the second type key relative to the keyway along the height direction of the keyway. The first and second sides are opposite sides.

Abstract: A lock core device based on matching the cross-sectional shape of a multiple key and a corresponding lock key, the lock contains a keyway, and the outer contour of the keyway is configured as a first section contour and a second section contour after superimposition, and its' a union outer contour. By adapting to existing keys with various cross-sectional profiles, the lock cylinder does not need to be manufactured separately according to the cross-sectional profile of the key, thus effectively reducing its manufacturing and inventory costs; A method for configuring a lock ball slot so that, in response to the deviation of the position of the teeth of the keys with different cross-sectional profiles, the teeth of the keys with different cross-sectional profiles can correspond to the lock ball slot for unlocking, thus ensuring stability and effectiveness during unlocking.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. The plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. A channel layer overlies the plurality of superlattice layers. An active layer overlies the channel layer. A first interlayer buffer layer is disposed directly between the first superlattice layer and the second superlattice layer. The first interlayer buffer layer comprises a first density of dislocations greater than a second density of dislocations in the first superlattice layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first transistor on a semiconductor substrate. The first transistor includes a first gate structure over the semiconductor substrate, a first pair of source/drain regions on opposing sides of the first gate structure, and a pair of diffusion barrier structures between the first pair of source/drain regions and a lower region of the semiconductor substrate. The first pair of source/drain regions comprise a first dopant. The diffusion barrier structures are co-doped with the first dopant and a second dopant different from the first dopant. A doping concentration of the first dopant within the first pair of source/drain regions is greater than a doping concentration of the first dopant within the diffusion barrier structures.

Abstract: A semiconductor structure includes a p-type doped III-V compound layer, a channel layer disposed over the p-type doped III-V compound layer, and a barrier structure. The channel layer includes an upper portion and a lower portion. The barrier structure is disposed between the upper portion of the channel layer and the lower portion of the channel layer. The barrier structure includes a first barrier layer, a second barrier layer and a third barrier layer. The first barrier layer is disposed between the second barrier layer and the third barrier layer. The channel layer has a first band gap, the first barrier layer has a second band gap, and the second barrier layer has a third band gap. The second band gap and the third band gap are greater than the first band gap.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Abstract: Depositing gallium nitride and carbon (GaN:C) (e.g., in the form of composite layers) when forming a gallium nitride drain of a transistor provides a buffer between the gallium nitride of the drain and silicon of a substrate in which the drain is formed. As a result, gaps and other defects caused by lattice mismatch are reduced, which improves electrical performance of the drain. Additionally, current leakage into the substrate is reduced, which further improves electrical performance of the drain. Additionally, or alternatively, implanting silicon in an aluminum nitride (AlN) liner for a gallium nitride drain reduces contact resistance at an interface between the gallium nitride and the silicon. As a result, electrical performance of the transistor is improved.

Abstract: A semiconductor package structure includes a control unit and a memory unit. The control unit includes a first wafer and a second wafer that are vertically stacked. The memory unit is disposed on the second wafer of the control unit. The memory unit includes multiple third wafers and a fourth wafer that are stacked vertically. The memory unit overlaps the control unit in a normal direction of the semiconductor package structure. In addition, a manufacturing method of the semiconductor package structure is provided.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.