Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: A semiconductor device includes a doped substrate and a seed layer in direct contact with the substrate. The seed layer includes a first seed sublayer having a first lattice structure. The first seed layer is doped with carbon. The seed layer further includes a second seed sublayer over the first see layer, wherein the second seed layer has a second lattice structure. The semiconductor device further includes a graded layer in direct contact with the seed layer. The graded layer includes a first graded sublayer including AlGaN having a first Al:Ga ratio; a second graded sublayer including AlGaN having a second Al:Ga ratio different from the first Al:Ga ratio; and a third graded sublayer over including AlGaN having a third Al:Ga ratio different from the second Al:Ga ratio. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer.

Abstract: A semiconductor package structure includes a control unit and a memory unit. The control unit includes a first wafer and a second wafer that are vertically stacked. The memory unit is disposed on the second wafer of the control unit. The memory unit includes multiple third wafers and a fourth wafer that are stacked vertically. The memory unit overlaps the control unit in a normal direction of the semiconductor package structure. In addition, a manufacturing method of the semiconductor package structure is provided.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

Abstract: A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element

Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: A semiconductor structure includes a III-V compound layer, a first barrier layer, a second barrier layer, and an active layer. The III-V compound layer includes a first region, a second region, and a third region. The second region is sandwiched between the first region and the third region. The first barrier layer is sandwiched between the first region and the second region, and the second barrier layer is sandwiched between the second region and the third region. The III-V compound layer includes a first band gap, the first barrier layer includes a second band gap, and the second barrier layer includes a third band gap. The second band gap and the third band gap are greater than the first band gap.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type. The semiconductor structure further includes a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type. The semiconductor structure further includes a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type. The semiconductor structure further includes an active layer over the fourth III-V layer. The semiconductor structure further includes a dielectric layer over the active layer.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.