Patents by Inventor Chi-Ming Wang
Chi-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6977844Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: GrantFiled: February 8, 2005Date of Patent: December 20, 2005Assignee: SanDisk CorporationInventors: Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Publication number: 20050219896Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations.Type: ApplicationFiled: April 6, 2004Publication date: October 6, 2005Inventors: Jian Chen, Chi-Ming Wang
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Publication number: 20050146933Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: ApplicationFiled: February 8, 2005Publication date: July 7, 2005Inventors: Daniel Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker Quader
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Publication number: 20050101236Abstract: A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.Type: ApplicationFiled: December 20, 2004Publication date: May 12, 2005Applicant: SanDisk CorporationInventors: Chi-Ming Wang, Kuo-Lung Chen, Shouchang Tsao
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Patent number: 6888752Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: GrantFiled: July 1, 2003Date of Patent: May 3, 2005Assignee: SanDisk CorporationInventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Patent number: 6801454Abstract: Techniques for producing and utilizing temperature compensated voltages to accurately read signals (e.g., voltages) representing data stored in memory cells of a memory system are disclosed. The memory system is, for example, a memory card. The magnitude of the temperature compensation can be varied or controlled in accordance with a temperature coefficient. These techniques are particularly well suited for used with memory cells that provide multiple levels of storage.Type: GrantFiled: October 1, 2002Date of Patent: October 5, 2004Assignee: SanDisk CorporationInventors: Yongliang Wang, Raul A. Cernea, Chi-Ming Wang
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Publication number: 20040109354Abstract: A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.Type: ApplicationFiled: December 6, 2002Publication date: June 10, 2004Applicant: SanDisk CorporationInventors: Chi-Ming Wang, Kuo-Lung Chen, Shouchang Tsao
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Publication number: 20040105311Abstract: Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.Type: ApplicationFiled: November 12, 2003Publication date: June 3, 2004Inventors: Raul-Adrian Cernea, Rushyah Tang, Douglas Lee, Chi-Ming Wang, Daniel Guterman
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Patent number: 6717851Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: GrantFiled: January 10, 2001Date of Patent: April 6, 2004Assignee: SanDisk CorporationInventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Publication number: 20040062085Abstract: Techniques for producing and utilizing temperature compensated voltages to accurately read signals (e.g., voltages) representing data stored in memory cells of a memory system are disclosed. The memory system is, for example, a memory card. The magnitude of the temperature compensation can be varied or controlled in accordance with a temperature coefficient. These techniques are particularly well suited for used with memory cells that provide multiple levels of storage.Type: ApplicationFiled: October 1, 2002Publication date: April 1, 2004Applicant: SanDisk CorporationInventors: Yongliang Wang, Raul A. Cernea, Chi-Ming Wang
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Publication number: 20040027865Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: ApplicationFiled: July 1, 2003Publication date: February 12, 2004Inventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Patent number: 6661708Abstract: Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.Type: GrantFiled: November 7, 2002Date of Patent: December 9, 2003Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Rushyah Tang, Douglas Lee, Chi-Ming Wang, Daniel Guterman
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Patent number: 6570785Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: GrantFiled: October 31, 2000Date of Patent: May 27, 2003Assignee: SanDisk CorporationInventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang
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Publication number: 20030072177Abstract: Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.Type: ApplicationFiled: November 7, 2002Publication date: April 17, 2003Inventors: Raul-Adrian Cernea, Rushyah Tang, Douglas Lee, Chi-Ming Wang, Daniel Guterman
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Patent number: 6490200Abstract: Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.Type: GrantFiled: August 7, 2001Date of Patent: December 3, 2002Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Rushyah Tang, Douglas Lee, Chi-Ming Wang, Daniel Guterman
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Publication number: 20020114184Abstract: Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are described. The various voltage levels can be produced by voltage generation circuitry (e.g., charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect, charge pump and/or regulator circuits are provided within at most one of the memory blocks of a memory system (unless back-ups are provided for fault tolerance), and a power bus is used to distribute the generated voltage levels to other of the memory blocks. According to another aspect, a memory controller generates multiple supply voltage levels that are distributed (e.g., via a power bus) to each of the memory blocks.Type: ApplicationFiled: February 16, 2001Publication date: August 22, 2002Applicant: SanDisk CorporationInventors: Geoffrey Steven Gongwer, Kevin M. Conley, Chi-Ming Wang, Yong Liang Wang, Raul Adrian Cernea
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Patent number: 6434044Abstract: Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are described. The various voltage levels can be produced by voltage generation circuitry (e.g., charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect, charge pump and/or regulator circuits are provided within at most one of the memory blocks of a memory system (unless back-ups are provided for fault tolerance), and a power bus is used to distribute the generated voltage levels to other of the memory blocks. According to another aspect, a memory controller generates multiple supply voltage levels that are distributed (e.g., via a power bus) to each of the memory blocks.Type: GrantFiled: February 16, 2001Date of Patent: August 13, 2002Assignee: SanDisk CorporationInventors: Geoffrey Steven Gongwer, Kevin M. Conley, Chi-Ming Wang, Yong Liang Wang, Raul Adrian Cernea
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Publication number: 20020051384Abstract: Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.Type: ApplicationFiled: August 7, 2001Publication date: May 2, 2002Applicant: SanDisk CorporationInventors: Raul-Adrian Cernea, Rushyah Tang, Douglas Lee, Chi-Ming Wang, Daniel Guterman
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Publication number: 20020051383Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.Type: ApplicationFiled: January 10, 2001Publication date: May 2, 2002Inventors: John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang, Khandker N. Quader
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Patent number: 6282120Abstract: Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.Type: GrantFiled: March 27, 2000Date of Patent: August 28, 2001Assignee: SanDisk CorporationInventors: Raul-Adrian Cernea, Rushyah Tang, Douglas Lee, Chi-Ming Wang, Daniel Guterman