Patents by Inventor Chi-Ming Wang

Chi-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160352327
    Abstract: Aspects of the disclosure provide a power circuit that includes a first switch module and a second switch module in parallel. The first switch module has a first gate terminal, a first drain terminal and a first source terminal, and the second switch module has a second gate terminal, a second drain terminal and a second source terminal. A drain interconnection module coupled to the first drain terminal and a gate interconnection module coupled to the second gate terminal are inductively coupled to balance current flowing through the first switch module and the second switch module.
    Type: Application
    Filed: May 28, 2015
    Publication date: December 1, 2016
    Applicant: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Chi-Ming WANG
  • Patent number: 9503079
    Abstract: Aspects of the disclosure provide a power circuit that includes a first switch module and a second switch module in parallel. The first switch module has a first gate terminal, a first drain terminal and a first source terminal, and the second switch module has a second gate terminal, a second drain terminal and a second source terminal. A drain interconnection module coupled to the first drain terminal and a gate interconnection module coupled to the second gate terminal are inductively coupled to balance current flowing through the first switch module and the second switch module.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: November 22, 2016
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Chi-Ming Wang
  • Publication number: 20160276817
    Abstract: An enclosure for breaking out a trunk cable includes: a base having a generally flat surface adapted for mounting to a mounting surface; a shell having a front and two side walls extending from opposite sides of the front and two opposed end walls, the side walls of the shell mounted to the base to form a cavity; a plurality of connectors mounted to each of the side walls; and a trunk cable routed into the cavity through one of the end walls, the trunk cable comprising a plurality of power conductors and/or a plurality of optical fibers. The power conductors and the optical fibers are connected with respective ones of the plurality of connectors.
    Type: Application
    Filed: March 16, 2016
    Publication date: September 22, 2016
    Inventor: Chi-ming Wang
  • Publication number: 20160247609
    Abstract: A grommet for mounting a cable within a cable gland includes: an annular body having first and second opposed ends along a longitudinal axis; and a flange extending radially outwardly from the first end of the body. The second end is tapered to encourage insertion into an open end of a cable gland. The flange and body are formed as a monolithic component comprising an elastomeric material.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 25, 2016
    Inventors: Chi-ming Wang, Ronald A. Vaccaro
  • Publication number: 20160163026
    Abstract: Systems and methods for Gaussian filter standard deviation variation. One embodiment of a method includes receiving a load current and a drain voltage associated with a switching converter that includes a Silicon Carbide (SiC) Mosfet transistor, determining a derivative of the drain voltage with respect to time, and calculating a switching loss associated with the switching converter. Some embodiments include predicting electromagnetic interference (EMI), selecting a Gaussian standard deviation from the switching loss, and determining a Gaussian switching voltage reference. Still some embodiments include adjusting a component of the SiC Mosfet transistor, based on the Gaussian standard deviation, and the Gaussian switching voltage reference to provide a desired switching loss.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 9, 2016
    Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: Chi-Ming Wang
  • Patent number: 9214861
    Abstract: A DC-to-DC, converter that can reduce a loss of the converter is provided. The DC-to-DC converter includes an inductor, a switching transistor connected to the inductor, and a controller that drives the transistor. The controller acquires a next step reference value for the DC-to-DC converter in a sampling time Ta. The next step reference value is expressed by an output voltage of the DC-to-DC converter or a flux linkage of the inductor. The controller determines interpolating points between a current state value that corresponds to the current reference value and the next step reference value in a sampling time Ts that is shorter than the sampling time Ta based on a loss of the DC-to-DC converter while changing from the current state value to the next step reference value. The controller supplies to the switching transistor the PWM signals with a duty that corresponds to each of the interpolating points.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 15, 2015
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Chi-Ming Wang, Masaki Wasekura, Robert D. Lorenz
  • Publication number: 20150219856
    Abstract: A device for connecting a hybrid trunk cable to one or more jumper cables includes: an enclosure having two opposed end walls and two opposed side walls; a power connector mounted to a first end wall; a fiber optic connector mounted to the first end wall; and a plurality of mixed media connectors mounted to a first side wall. The power connector is electrically connected to the plurality of mixed media connectors, and the fiber optic connector is optically connected to the plurality of mixed media connectors.
    Type: Application
    Filed: July 31, 2014
    Publication date: August 6, 2015
    Inventor: Chi-ming Wang
  • Publication number: 20150002121
    Abstract: A DC-to-DC, converter that can reduce a loss of the converter is provided. The DC-to-DC converter includes an inductor, a switching transistor connected to the inductor, and a controller that drives the transistor. The controller acquires a next step reference value for the DC-to-DC converter in a sampling time Ta. The next step reference value is expressed by an output voltage of the DC-to-DC converter or a flux linkage of the inductor. The controller determines interpolating points between a current state value that corresponds to the current reference value and the next step reference value in a sampling time Ts that is shorter than the sampling time Ta based on a loss of the DC-to-DC converter while changing from the current state value to the next step reference value. The controller supplies to the switching transistor the PWM signals with a duty that corresponds to each of the interpolating points.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Applicants: WISCONSIN ALUMNI RESEARCH FOUNDATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Chi-Ming WANG, Masaki WASEKURA, Robert D. LORENZ
  • Patent number: 8884357
    Abstract: A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: November 11, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Chi-Ming Wang, Johann Alsmeier, Henry Chien, Xiying Costa, Yung-Tin Chen, Christopher Petti
  • Publication number: 20140284697
    Abstract: A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 25, 2014
    Applicant: SanDisk Technologies, Inc.
    Inventors: Chi-Ming Wang, Johann Alsmeier, Henry Chien, Xiying Costa, Yung-Tin Chen, Christopher Petti
  • Publication number: 20140264525
    Abstract: A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: SanDisk Technologies, Inc.
    Inventors: Akira Takahashi, Chi-Ming Wang, Johann Alsmeier, Henry Chien, Xiying Costa
  • Patent number: 8228729
    Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 24, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Bo Liu, Yan Li, Alexander Kwok-Tung Mak, Chi-Ming Wang, Eugene Jinglun Tam, Kwang-Ho Kim
  • Publication number: 20120113716
    Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.
    Type: Application
    Filed: December 21, 2011
    Publication date: May 10, 2012
    Inventors: Bo Liu, Yan Li, Alexander Kwok-Tung Mak, Chi-Ming Wang, Eugene Jinglun Tam, Kwang-ho Kim
  • Patent number: 8169831
    Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: May 1, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Hao Thai Nguyen, Man Lung Mui, Seungpil Lee, Fanglin Zhang, Chi-Ming Wang
  • Patent number: 8102705
    Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: January 24, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Bo Liu, Yan Li, Alexander Kwok-Tung Mak, Chi-Ming Wang, Eugene Jinglun Tam, Kwang-ho Kim
  • Publication number: 20110205804
    Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Inventors: Hao Thai Nguyen, Man Lung Mui, Seungpil Lee, Fanglin Zhang, Chi-Ming Wang
  • Patent number: 7957197
    Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result of the sensing to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, by which current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination of the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of this determination; and a transfer gate coupled to the data latch to supply a latched result to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: June 7, 2011
    Assignee: SanDisk Corporation
    Inventors: Hao Thai Nguyen, Man Lung Mui, Seungpil Lee, Fanglin Zhang, Chi-Ming Wang
  • Publication number: 20100309720
    Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented.
    Type: Application
    Filed: December 10, 2009
    Publication date: December 9, 2010
    Inventors: Bo Liu, Yan Li, Alexander Kwok-Tung Mak, Chi-Ming Wang, Eugene Jinglun Tam, Kwang-ho Kim
  • Publication number: 20090296488
    Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 3, 2009
    Inventors: Hao Thai Nguyen, Man Lung Mui, Seungpil Lee, Fanglin Zhang, Chi-Ming Wang
  • Patent number: D701509
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: March 25, 2014
    Assignee: Motorola Solutions, Inc.
    Inventors: Carl DeGiovine, Sunghun Lim, Robert A. Spano, Chi-Ming Wang