Abstract: Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.

Abstract: The present invention relates to a trackball/actuator assembly for a portable computer that includes one or more free pivot-arm key plates disposed around a trackball module. According to one embodiment of the present invention, it includes a housing having a top surface and sidewalls extending downward from opposite ends of the top surface, a first keyplate protruding from the top surface between the sidewalls, a second keyplate protruding from the top surface between the sidewalls, and a trackball disposed between the keyplates. First and second pivot joints formed integral to the first and second sidewalls, respectively, form a first horizontal axis between the sidewalls that is offset from the first keyplate. The first keyplate is rotatably coupled to first and second pivot joints so that it pivots freely about the first horizontal axis.

Abstract: A negative voltage decoder applies a negative voltage to the sense line of a selected row of a memory array but not to sense lines of unselected rows. The negative voltage decoder includes a negative voltage source, an array of P-channel transistors, and a negative voltage address signal generator. P-channel transistors in the array have gates coupled to address lines, so that address signals on the address lines turn on the P-channel transistors and connect only the selected sense line to the negative voltage source. A negative voltage charge pumps in the negative voltage address signal generator generates address signals lower than the negative voltage source. In one embodiment, the transistor array has rows of P-channel transistors which fit the pitch of the memory array and individual P-channel transistors which are stacked laterally away from the memory array, and each row of P-channel transistors couples through a set of individual transistor to a set of sense lines.