Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.

Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.

Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.

Abstract: A semiconductor package device comprises a substrate, an electronic component and a protection layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a first opening penetrating the substrate. The electronic component is disposed on the first surface of the substrate. The protection layer is disposed on the second surface of the substrate. The protection layer has a first portion adjacent to the first opening and a second portion disposed farther away from the first opening than is the first portion of the protection layer. The first portion of the protection layer has a surface facing away from the second surface of the substrate. The second portion of the protection layer has a surface facing away from the second surface of the substrate.

Abstract: A semiconductor device package is provided, which includes a carrier, a first reflective element, a second reflective element, a first optical component, a second optical component and a microelectromechanical system (MEMS) device. The carrier has a first surface. The first reflective element is disposed on the first surface of the carrier. The second reflective element disposed on the first surface of the carrier. The first optical component is disposed on the first reflective element. The second optical component is disposed on the second reflective element. The MEMS device is disposed on the first surface of the carrier to provide light beams to the first reflective element and the second reflective element. The light beams provided to the first reflective element are reflected to the first optical component and the light beams provided to the second reflective element are reflected to the second optical component.

Abstract: An image sensor comprises a chip, a first redistribution layer (RDL), a second RDL and a third RDL. The chip has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first RDL is disposed on the first surface of the chip and extends along the first surface of the chip and beyond the lateral surface of the chip. The second RDL is disposed on the second surface of the chip. The third RDL is disposed on the lateral surface of the chip and connects the first RDL to the second RDL.

Abstract: A semiconductor package device comprises a substrate, an electronic component and a protection layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a first opening penetrating the substrate. The electronic component is disposed on the first surface of the substrate. The protection layer is disposed on the second surface of the substrate. The protection layer has a first portion adjacent to the first opening and a second portion disposed farther away from the first opening than is the first portion of the protection layer. The first portion of the protection layer has a surface facing away from the second surface of the substrate. The second portion of the protection layer has a surface facing away from the second surface of the substrate.

Abstract: An image sensor comprises a chip, a first redistribution layer (RDL), a second RDL and a third RDL. The chip has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first RDL is disposed on the first surface of the chip and extends along the first surface of the chip and beyond the lateral surface of the chip. The second RDL is disposed on the second surface of the chip. The third RDL is disposed on the lateral surface of the chip and connects the first RDL to the second RDL.

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.

Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract: A speaker assembly is configured for assembly to a housing. The housing defines a through hole and a receiving groove communicating with each other. The speaker assembly includes a speaker and a speaker cover. The speaker is received in the through hole. The speaker cover has an extending edge beyond a peripheral wall of the speaker and is received in the receiving groove.

Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.

Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: The present invention provides a resistor structure including a substrate, an ILD layer, a transistor and a resistor. The substrate includes a resistor region and an active region. The ILD layer is disposed directly on the substrate. The transistor is disposed in the active region in the ILD layer wherein the transistor includes a metal gate. The resistor is disposed in the resistor region above the ILD layer, wherein the resistor directly contacts the ILD layer.

Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.