Patents by Inventor Chi Sheng Tseng

Chi Sheng Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8524556
    Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: September 3, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
  • Publication number: 20130168816
    Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Shu-Hsuan Chih, Po-Kuang Hsieh, Chia-Chen Sun, Po-Cheng Huang, Shih-Chieh Hsu, Chi-Horn Pai, Yao-Chang Wang, Jie-Ning Yang, Chi-Sheng Tseng, Po-Jui Liao, Kuang-Hung Huang, Shih-Chang Chang
  • Patent number: 8477006
    Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 2, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Jie-Ning Yang, Shih-Chieh Hsu, Chun-Hsien Lin, Yao-Chang Wang, Chi-Horn Pai, Chi-Sheng Tseng
  • Publication number: 20130102145
    Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Inventors: Kuang-Hung Huang, Po-Jui Liao, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang
  • Publication number: 20130099307
    Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer in the first gate trench, forming a second work function metal layer in the first gate trench and the second gate trench, forming a first patterned mask layer exposing portions of the second work function metal layer in the first gate trench and the second gate trench, and performing an etching process to remove the exposed second work function metal layer.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Inventors: Chi-Sheng Tseng, Jie-Ning Yang, Kuang-Hung Huang, Yao-Chang Wang, Po-Jui Liao, Shih-Chieh Hsu
  • Publication number: 20130049924
    Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Inventors: Jie-Ning Yang, Shih-Chieh Hsu, Chun-Hsien Lin, Yao-Chang Wang, Chi-Horn Pai, Chi-Sheng Tseng
  • Publication number: 20130049168
    Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Inventors: Jie-Ning Yang, Shih-Chieh Hsu, Yao-Chang Wang, Chi-Horn Pai, Chi-Sheng Tseng, Kun-Szu Tseng, Ying-Hung Chou, Chiu-Hsien Yeh
  • Publication number: 20090186475
    Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.
    Type: Application
    Filed: January 21, 2008
    Publication date: July 23, 2009
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Shih-Chieh Hsu, Chih-Chiang Wu, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Wen-Han Hung, Yao-Chin Cheng, Chi-Sheng Tseng, Yu-Ming Lin, Shih-Jung Tu, Tzyy-Ming Cheng
  • Patent number: D274469
    Type: Grant
    Filed: June 29, 1981
    Date of Patent: June 26, 1984
    Inventors: Tien Huang, Chi Sheng Tseng, Chifuyu Funatsuki, Etsudo Tatsumi