Patents by Inventor Chi Shun Lo

Chi Shun Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10116285
    Abstract: A method includes forming a replica circuit above a surface of a glass-type material. The replica circuit includes a thin-film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The method further includes forming a transformer above the surface of the glass-type material. The transformer is coupled to the replica circuit, and the transformer is configured to facilitate an impedance match between the replica circuit and an antenna.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Patent number: 10002700
    Abstract: In a particular embodiment, a device includes a low-loss substrate, a first inductor structure, and an air-gap. The first inductor structure is between the low-loss substrate and a second inductor structure. The first inductor structure is aligned with the second inductor structure to form a transformer. The air-gap is between the first inductor structure and the second inductor structure.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: June 19, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, John H. Hong
  • Publication number: 20170134007
    Abstract: A method includes forming a replica circuit above a surface of a glass-type material. The replica circuit includes a thin-film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The method further includes forming a transformer above the surface of the glass-type material. The transformer is coupled to the replica circuit, and the transformer is configured to facilitate an impedance match between the replica circuit and an antenna.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Patent number: 9634645
    Abstract: A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Patent number: 9496255
    Abstract: A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Changhan Yun, Sang-June Park, Chi Shun Lo, Mario F. Velez, Jonghae Kim
  • Patent number: 9431510
    Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Yun, Chengjie Zuo, Chi Shun Lo, Jonghae Kim, Mario F. Velez
  • Patent number: 9431473
    Abstract: Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chi Shun Lo, Je-Hsiung Lan, Mario Francisco Velez, Jonghae Kim
  • Patent number: 9379802
    Abstract: A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 28, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Changhan Yun, Chi Shun Lo, Mario F. Velez, Jonghae Kim
  • Patent number: 9363902
    Abstract: This disclosure provides implementations of inductors, transformers, and related processes. In one aspect, a device includes a substrate having first and second surfaces. A first inducting arrangement includes a first set of vias, a second set of vias, a first set of traces arranged over the first surface connecting the first and second vias, and a second set of traces arranged over the second surface connecting the first and second vias. A second inducting arrangement is inductively-coupled and interleaved with the first inducting arrangement and includes a third set of vias, a fourth set of vias, a third set of traces arranged over the first surface connecting the third and fourth vias, and a fourth set of traces arranged over the second surface connecting the third and fourth vias. One or more sets of dielectric layers insulate portions of the traces from one another.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 7, 2016
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chi Shun Lo, Jonghae Kim, Chengjie Zuo, Changhan Hobie Yun
  • Patent number: 9331666
    Abstract: This disclosure provides systems, methods and apparatus related to acoustic resonators that include composite transduction layers for enabling selective tuning of one or more acoustic or electromechanical properties. In one aspect, a resonator structure includes one or more first electrodes, one or more second electrodes, and a transduction layer arranged between the first and second electrodes. The transduction layer includes a plurality of constituent layers. In some implementations, the constituent layers include one or more first piezoelectric layers and one or more second piezoelectric layers. The transduction layer is configured to, responsive to signals provided to the first and second electrodes, provide at least a first mode of vibration of the transduction layer with a displacement component along the z axis and at least a second mode of vibration of the transduction layer with a displacement component along the plane of the x axis and they axis.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 3, 2016
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chengjie Zuo, Jonghae Kim, Changhan Hobie Yun, Sang-June Park, Philip Jason Stephanou, Chi Shun Lo, Robert Paul Mikulka, Mario Francisco Velez, Ravindra V. Shenoy, Matthew Michael Nowak
  • Patent number: 9270254
    Abstract: Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: February 23, 2016
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chengjie Zuo, Changhan Yun, Chi Shun Lo, Wesley Nathaniel Allen, Mario Francisco Velez, Jonghae Kim, Sanghoon Joo
  • Patent number: 9130505
    Abstract: A multiple frequency reconfigurable voltage controlled oscillator (VCO) (136) includes a variable capacitance device (112), an inductor (116) coupled in parallel with the variable capacitance device (112), and at least two circuit paths (118, 120, 122) coupled in parallel with the variable capacitance device (112) and the inductor (116). The circuit paths (118, 120, 122) each include a piezoelectric laterally vibrating resonator (126, 130, 134) and a switch (124, 128, 132) for selectably coupling each piezoelectric laterally vibrating resonator (126, 130, 134) in parallel with the inductor (116) and variable capacitance device (112).
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 8, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Changhan Yun, Chi Shun Lo, Jonghae Kim
  • Patent number: 9099986
    Abstract: Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: August 4, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chengjie Zuo, Changhan Yun, Chi Shun Lo, Wesley Nathaniel Allen, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20150215026
    Abstract: A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
    Type: Application
    Filed: April 10, 2015
    Publication date: July 30, 2015
    Inventors: Chengjie Zuo, Changhan Hobie Yun, Chi Shun Lo, Mario Francisco Velez, Jonghae Kim
  • Patent number: 9083300
    Abstract: This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a contour mode resonator device includes a first conductive layer with a plurality of first layer electrodes including a first electrode at which a first input signal can be provided and a second electrode at which a first output signal can be provided. A second conductive layer includes a plurality of second layer electrodes including a first electrode proximate the first electrode of the first conductive layer and a second electrode proximate the second electrode of the first conductive layer. A second signal can be provided at the first electrode or the second electrode of the second conductive layer to cooperate with the first input signal or the first output signal to define a differential signal. A piezoelectric layer is disposed between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: July 14, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chi Shun Lo, Jonghae Kim, Sang-June Park, Sanghoon Joo, Chengjie Zuo, Changhan Yun
  • Publication number: 20150118819
    Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
    Type: Application
    Filed: November 26, 2014
    Publication date: April 30, 2015
    Inventors: Changhan Hobie YUN, Chengjie ZUO, Chi Shun LO, Jonghae KIM, Mario Francisco VELEZ
  • Patent number: 9008602
    Abstract: A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: April 14, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Changhan Yun, Chi Shun Lo, Mario F. Velez, Jonghae Kim
  • Patent number: 9001031
    Abstract: This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 7, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chi Shun Lo, Je-Hsiung Jeffrey Lan, Mario Francisco Velez, Robert Paul Mikulka, Chengjie Zuo, Changhan Hobie Yun, Jonghae Kim
  • Patent number: 8987976
    Abstract: A method and apparatus for a piezoelectric resonator having combined thickness and width vibrational modes are disclosed. A piezoelectric resonator may include a piezoelectric substrate and a first electrode coupled to a first surface of the piezoelectric substrate. The piezoelectric resonator may further include a second electrode coupled to a second surface of the piezoelectric substrate, where the first surface and the second surface are substantially parallel and define a thickness dimension of the piezoelectric substrate. Furthermore, the thickness dimension and the width dimension of the piezoelectric substrate are configured to produce a resonance from a coherent combination of a thickness vibrational mode and a width vibrational mode when an excitation signal is applied to the electrodes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Chi Shun Lo, Sanghoon Joo, Changhan Yun, Jonghae Kim
  • Patent number: 8970516
    Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 3, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Justin Phelps Black, Ravindra V. Shenoy, Evgeni Petrovich Gousev, Aristotele Hadjichristos, Thomas Andrew Myers, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Chi Shun Lo