Abstract: The present invention relates to a field emission display in which a gate plate having a gate hole and a gate electrode around the gate hole is formed between an anode plate having phosphor and a cathode plate having a field emitter and a control device for controlling field emission current, wherein the field emitter of the cathode plate is constructed to be opposite to the phosphor of the anode plate through the gate hole. According to the present invention, it is possible to significantly reduce the display row/column driving voltage by applying scan and data signals of the field emission display to the control device of each pixel, And the present invention is directed to improve the brightness of the field emission display in such a manner that the electric field necessary for field emission is applied through the gate electrode of the gate plate to freely control the distance between the anode plate and the cathode plate, so that a high voltage can be applied to the anode.

Abstract: A field emission device including a cathode having an electric field emitter for emitting electrons, a field emission inducing gate for inducing electron emission, and an anode for receiving the emitted electrons. A field emission suppressing gate is interposed between the cathode and the field emission inducing gate for suppressing electron emission, so that problems such as gate leakage current, electron emission due to anode voltage, and electron beam spreading of the conventional field emission device are significantly overcome.

Abstract: Provided is a field emission display in which a gate hole having an inclined inner wall and a gate electrode around the gate hole are formed between an anode plate having a phosphor and a cathode plate having a field emitter and a control device for controlling a field emission current, whereby the voltage applied to the gate electrode of the gate plate serves to prohibit an electron emission of the field emitter by the anode voltage, and prevent a local arching by forming a totally uniform potential, so that the life time of the field emission display can be improved, and the gate hole having the inclined inner wall enables a fabrication of a filed emission display panel having a high brightness without an additional focusing grid.

Abstract: Provided is an apparatus for measuring a picture and a lifetime of a display panel including: a chamber having at least one display panel for measurement disposed therein, and for uniformly maintaining temperature and humidity conditions of an inner portion; at least one camera installed in the chamber to obtain image signals of the display panel; a bias supply and measurement part for providing pulse bias voltage and current required to measure depending on control signals, and measuring the voltage and current to convert into digital data when the display panel is driven; a converter for converting the image signals obtained through the camera into digital data; and a control and data processing part for generating parameters by receiving the digital data from the bias supply and measurement part and the converter, and analyzing a lifetime of the display panel using the parameters.

Abstract: An active matrix organic light emitting diode display panel circuit capable of reducing current and brightness nonuniformities between pixels by including a threshold voltage compensation circuit block between a data line and the pixels is provided. The threshold voltage of a video signal loaded in a data line is compensated for while the video signal passes through the threshold voltage compensation circuit block and then provided to a driving transistor of the pixels. One threshold voltage compensation circuit block is connected commonly to a plurality of pixels, rather than be connected to every pixel, so that threshold voltage compensation can be achieved for high-quality, large-sized displays, without increasing the number of transistors for the pixels.

Abstract: Provided is a field emission display, which includes: a cathode portion including row signal lines and column signal lines in a stripe form allowing matrix addressing to be carried out on a substrate, and pixels defined by the row signal lines and the column signal lines, each pixel having a field emitter and a control device which controls the field emitter with two terminals connected to at least the row signal line and the column signal line and one terminal connected to the field emitter; an anode portion having an anode electrode, and a phosphor connected to the anode electrode; and a gate portion having a metal mesh with a plurality of penetrating holes, and a dielectric layer formed on at least one region of the metal mesh, wherein the gate portion is disposed between the cathode portion and the anode portion to allow the surface where the dielectric layer is formed to be faced to the cathode portion and to allow electrons emitted from the field emitter to collide with the phosphor via the penetrating

Abstract: Provided is a field emission device having a mesh gate. The object of this research is to provide a field emission display (FED) using a triode field emission device for preventing increase of operation voltage, and securing high concentration of electron beams. The operation properties of the FED is different based on a structure of an extraction electrode. In this research, the extraction electrode is formed on the electron emitting source and it has a plurality of openings corresponding to the locations of carbon nanotube mixture. The concentration of the electron beams is raised and leakage current is suppressed by using an insulating mesh gate plate. The upper part of the openings has a smaller diagram than the lower part. The high concentration of electron beams and little leakage current can be generated by adding auxiliary electrodes or optimizing the shape of electrodes.

Abstract: The present invention relates to a field emission display in which a gate plate having a gate hole and a gate electrode around the gate hole is formed between an anode plate having phosphor and a cathode plate having a field emitter and a control device for controlling field emission current, wherein the field emitter of the cathode plate is constructed to be opposite to the phosphor of the anode plate through the gate hole.

Abstract: Provided is a field emission device having a mesh gate. The object of this research is to provide a field emission display (FED) using a triode field emission device for preventing increase of operation voltage, and securing high concentration of electron beams. The operation properties of the FED is different based on a structure of an extraction electrode. In this research, the extraction electrode is formed on the electron emitting source and it has a plurality of openings corresponding to the locations of carbon nanotube mixture. The concentration of the electron beams is raised and leakage current is suppressed by using an insulating mesh gate plate. The upper part of the openings has a smaller diagram than the lower part. The high concentration of electron beams and little leakage current can be generated by adding auxiliary electrodes or optimizing the shape of electrodes.

Abstract: The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line.

Abstract: The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line.

Abstract: An active matrix organic light emitting diode display panel circuit capable of reducing current and brightness nonuniformities between pixels by including a threshold voltage compensation circuit block between a data line and the pixels is provided. The threshold voltage of a video signal loaded in a data line is compensated for while the video signal passes through the threshold voltage compensation circuit block and then provided to a driving transistor of the pixels. One threshold voltage compensation circuit block is connected commonly to a plurality of pixels, rather than be connected to every pixel, so that threshold voltage compensation can be achieved for high-quality, large-sized displays, without increasing the number of transistors for the pixels.

Abstract: A high-resolution field emission display that applies a field emission device (or a field emission array) being an electron source element to a flat panel display device. The field emission display includes an upper plate and a lower plate that face each other, wherein the lower plate and the upper plate are vacuum-packaged in parallel positions. A dot pixel of the lower plate includes a high-voltage amorphous silicon thin film transistor formed on the glass substrate of the lower plate, a diode type field emission film partially formed on the drain of the high-voltage amorphous silicon TFT, a passivation insulation layer formed on the high-voltage amorphous silicon TFT and the lateral side of the diode type field emission film, and an electron beam focusing electrode/light-shading film which vertically overlaps with the high-voltage amorphous silicon TFT on some parts of the passivation insulation layer and is formed on a lateral side of the diode type field emission film.

Abstract: A cathode structure for a field emission device, which is an essential component of a field emission device, and a method of fabricating the same are provided. An emitter material for electron emission constituting cathodes is formed in a particulate emitter, the particulate emitter is formed of a material from which electrons can be easily emitted at a low electric field. A significant advantage of the present invention over a conventional art is that the present invention patterns an emitter material to a cathode electrode using a photolithography process or a lift-off process. In the lift-off process, the emitting compound is patterned using a sacrifice layer. Also, in another embodiment of the present invention, there is disclosed a method of easily fabricating cathodes for a triode-type field emission device using a particulate emitter material at a low process temperature.

Abstract: The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line.

Abstract: The present invention provides a field emission device driven with a high voltage. The field emission device of the present invention includes a resistor connected between a gate electrode and an external terminal to prevent a leakage current by an electrical connection between the gate electrode and the emitter. Therefore, the power consumption of the device is decreased and the operating characteristic of the device is improved.

Abstract: The present invention provides a field emission device driven with a high voltage. The field emission device of the present invention includes a resistor connected between a gate electrode and an external terminal to prevent a leakage current by an electrical connection between the gate electrode and the emitter. Therefore, the power consumption of the device is decreased and the operating characteristic of the device is improved.

Abstract: A high-resolution field emission display that applies a field emission device(or a field emission array) being an electron source element to a flat panel display device. The field emission display includes an upper plate and a lower plate that fac each other, wherein the lower plate and the upper plate are vacuum-packaged in parallel positions. A dot pixel of the lower plate includes a high-voltage amorphous silicon thin film transistor formed on the glass substrate of the lower plate, a diode type field emission film partially formed on the drain of the high-voltage amorphous silicon TFT, a passivation insulation layer formed on the high-voltage amorphous silicon TFT and the lateral side of the diode type field emission film, and an electron beam focusing electrode/light-shading film which vertically overlaps with the high-voltage amorphous silicon TFT on some parts of the passivation insulation layer and is formed on a lateral side of the diode type field emission film.

Abstract: A cathode structure for a field emission device, which is an essential component of a field emission device, and a method of fabricating the same are provided. An emitter material for electron emission constituting cathodes is formed in a particulate emitter, the particulate emitter is formed of a material from which electrons can be easily emitted at a low electric field. A significant advantage of the present invention over a conventional art is that the present invention patterns an emitter material to a cathode electrode using a photolithography process or a lift-off process. In the lift-off process, the emitting compound is patterned using a sacrifice layer. Also, in another embodiment of the present invention, there is disclosed a method of easily fabricating cathodes for a triode-type field emission device using a particulate emitter material at a low process temperature.

Abstract: The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line.