Patents by Inventor Chi-Sun Hwang

Chi-Sun Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9196689
    Abstract: The present invention relates to thin films comprising non-stoichiometric monoxides of: copper (OCu2)x with embedded cubic metal copper (Cucy) [(OCu2)x+(Cu1-2)y, wherein 0.05?x<1 and 0.01?y?0.9]; of tin (OSn)?x with embedded metal tin (Sn?x) [(OSn)z+(Sn1-2)w wherein 0.05?z<1 and 0.01?w?0.9]; Cucx—Sn?x alloys with embedded metal Sn and Cu [(O—Cu—Sn)a+(Cu?—Sn?)b with 0<?<2 and 0<?<2, wherein 0.05?a<1 and 0.01?b?0.9]; and of nickel (ONi)x with embedded Ni and Sn species [(O—Ni)a+(Ni?—Sn?)b with 0<?<2 and 0<?<2, wherein 0.05?a<1 and 0.01?b?0.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: November 24, 2015
    Assignees: FACULDADE DE CIENCIAS E TECHNOLOGIA DA UNIVERSIDADE NOVA DE LISBOA, ELECTRONIC AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Elvira Maria Correia Fortunato, Rodrigo Ferrão De Paiva Martins, Ana Raquel Xarouco De Barros, Nuno Filipe De Oliveira Correia, Vitor Manuel Loureiro Figueiredo, Pedro Miguel Cândido Barquinha, Sang-Hee Ko Park, Chi-Sun Hwang
  • Publication number: 20150323817
    Abstract: Provided are a spatial light modulator (SLM) and a method of fabricating the same. The complex spatial light modulator includes a thin film transistor (TFT) layer provided on a substrate, an amplitude type SLM and a phase type SLM electrically connected to the TFT layer, and a first polarizer provided on the phase type SLM, wherein the TFT layer includes transistors electrically connected to the amplitude type SLM and the phase type SLM, respectively, and the amplitude type SLM and the phase type SLM are commonly and electrically connected to the TFT layer and driven.
    Type: Application
    Filed: September 30, 2014
    Publication date: November 12, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Hae KIM, Chi-Sun HWANG, Gi Heon KIM, Hojun RYU, Chunwon BYUN, Himchan OH, Myung Lae LEE, Hye Yong CHU
  • Publication number: 20150318363
    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
    Type: Application
    Filed: July 15, 2015
    Publication date: November 5, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Haeng CHO, Sang-Hee PARK, Chi-Sun HWANG
  • Publication number: 20150236169
    Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, FACULTY OF SCIENCE AND TECHNOLOGY NEW UNIVERSITY OF LISBON
    Inventors: Sang Hee PARK, Chi Sun HWANG, Chun Won BYUN, Elvira M.C. FORTUNATO, Rodrigo F.P. MARTINS, Ana R.X. BARROS, Nuno F.O. CORREIA, Pedro M.C. BARQUINHA, Vitor M.L. FIGUEIREDO
  • Publication number: 20150225845
    Abstract: Provided is a metal oxide thin film forming method including: vaporizing a first metal oxide precursor; allowing the vaporized first metal oxide precursor to flow into a mixture chamber by using a first carrier gas; injecting the flowed first metal oxide precursor on a substrate through a micro nozzle connected to the mixture chamber to form a first metal oxide precursor layer on the substrate; and emitting electromagnetic waves to the first metal oxide precursor layer to form a first metal oxide layer.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 13, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jonghyurk PARK, Jong-Heon YANG, Seunghyup YOO, Jungmin CHOI, Hye Yong CHU, Chi-Sun HWANG
  • Patent number: 9105726
    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 11, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Haeng Cho, Sang-Hee Park, Chi-Sun Hwang
  • Patent number: 9099991
    Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: August 4, 2015
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.
    Inventors: Sang Hee Park, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyung Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
  • Publication number: 20150214250
    Abstract: Provided are a display device, a method of fabricating the display device, and a method of fabricating an image sensor device. The method of fabricating the display device includes preparing a substrate including a cell array area and a peripheral circuit area, forming a silicon layer on the peripheral circuit area of the substrate, forming oxide layers on the cell array area and the peripheral circuit area of the substrate, forming gate dielectric layers on the silicon layer and the oxide layers, forming the gate electrodes on the gate dielectric layers, wherein the gate electrodes expose both ends of the silicon layer and both ends of the oxide layers, and injecting dopant into both ends of the silicon layer and both ends of the oxide layers at the same time.
    Type: Application
    Filed: July 30, 2014
    Publication date: July 30, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jong-Heon YANG, Jonghyurk PARK, Chunwon BYUN, Chi-Sun HWANG
  • Publication number: 20150171833
    Abstract: Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.
    Type: Application
    Filed: July 18, 2014
    Publication date: June 18, 2015
    Applicants: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp
    Inventors: Jae-Eun PI, Sang-Hee PARK, Min Ki RYU, Chi-Sun HWANG, OhSang KWON, Eunsuk PARK, Kee-Chan PARK, YeonKyung KIM
  • Publication number: 20150160511
    Abstract: Provided is a display device and a method of manufacturing the same. The display device includes a reflective display part including a first cathode electrode and a first anode electrode and a liquid crystal layer, a light emitting display part including a second cathode electrode and a second anode electrode and a light emission film, and a thin film transistor part being electrically connected to the first and second anode electrodes. The light emitting display part further includes a bank disposed on one side of the second anode electrode between the second anode electrode and the light emission film.
    Type: Application
    Filed: May 23, 2014
    Publication date: June 11, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Hae KIM, Gi Heon KIM, Hojun RYU, Chi-Sun HWANG, Jong-Heon YANG, Sang Chul LIM, Jae Bon KOO, Jonghee LEE, Jeong Ik LEE
  • Patent number: 9053937
    Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: June 9, 2015
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, FACULTY OF SCIENCE AND TECHNOLOGY NEW UNIVERSITY OF LISBON
    Inventors: Sang Hee Park, Chi Sun Hwang, Chun Won Byun, Elvira M. C. Fortunato, Rodrigo F. P. Martins, Ana R. X. Barros, Nuno F. O. Correia, Pedro M. C. Barquinha, Vitor M. L. Figueiredo
  • Patent number: 9035688
    Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 19, 2015
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.
    Inventors: Jae-Eun Pi, Kee-Chan Park, Sangyeon Kim, Joondong Kim, Yeon Kyung Kim, HongKyun Lym, Sang-Hee Park, Byoung Gon Yu, Chi-Sun Hwang, Jong Woo Kim, OhSang Kwon, Min Ki Ryu
  • Publication number: 20150084995
    Abstract: Provided is a display device. The display device includes: a pixel including an emissive element circuit, a reflective element circuit, and a switch transistor selecting one of the emissive element circuit and the reflective element circuit; an illumination sensor generating an illumination information signal according to an illumination of an external light source by detecting the external light source; and a controller generating control signals for driving the pixel according to pixel data, wherein the controller generates a light signal controlling the switch transistor by referencing the illumination information signal.
    Type: Application
    Filed: March 13, 2014
    Publication date: March 26, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyunkoo Lee, Jae-Eun Pi, Chi-Sun Hwang, Jong-Heon Yang
  • Patent number: 8987718
    Abstract: Disclosed are dual mode display devices and methods of manufacturing the same. The dual mode display device may include a first substrate, a first electrode on the first substrate, a second substrate opposite to the first electrode and the first substrate, a second electrode between the second substrate and the first electrode, a third electrode between the first electrode and the second electrode, an optic switching layer between the first electrode and the third electrode, and an organic light-emitting layer between the second electrode and the third electrode.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: March 24, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Bon Koo, Hojun Ryu, Chi-Sun Hwang, Jeong Ik Lee, Hye Yong Chu
  • Publication number: 20140367689
    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
    Type: Application
    Filed: February 27, 2014
    Publication date: December 18, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Haeng CHO, Sang-Hee PARK, Chi-Sun HWANG
  • Patent number: 8901548
    Abstract: Provided is a dual-mode display including a substrate, and a plurality of sub pixels on the substrate. Each of the sub pixels may include an emissive device, a reflective optical filter provided on a surface of the emissive device, and an optical shutter provided on other surface of the emissive device.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 2, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joon Tae Ahn, Jeong Ik Lee, Jaehyun Moon, Seung Koo Park, Nam Sung Cho, Doo-Hee Cho, Jun-Han Han, Joo Hyun Hwang, Jin Wook Shin, Jong Tae Lim, Chul Woong Joo, Jin Woo Huh, Chi-Sun Hwang, Hojun Ryu, Jae Bon Koo, Hye Yong Chu
  • Publication number: 20140333977
    Abstract: Provided is a display device. The display device includes a backlight unit generating a plurality of flat lights and a spatial light modulator (SLM) unit generating an interference pattern by using the plurality of lights according to hologram data and displaying a hologram based on the generated interference pattern. The backlight unit is manufactured as an organic light emitting diode including a plurality of quantum dots.
    Type: Application
    Filed: March 14, 2014
    Publication date: November 13, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Chi-Sun HWANG, Hye Yong CHU, Jong Sool JEONG
  • Patent number: 8841665
    Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: September 23, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Hee Park, Min Ki Ryu, Him Chan Oh, Chi Sun Hwang
  • Publication number: 20140159036
    Abstract: According to example embodiments of the inventive concept, provided is a transistor with a nano-layered oxide semiconductor layer. The oxide semiconductor layer may include at least one first nano layer and at least one second nano layer that are alternatingly stacked one on another. Here, the first nano layer and the second nano layer may include different materials from each other, and thus, a channel with high electron mobility may be formed at the interface between the first and second nano layers. Accordingly, the transistor can have high reliability.
    Type: Application
    Filed: September 6, 2013
    Publication date: June 12, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Su Jae LEE, Chi-Sun HWANG, Hye Yong CHU, Sang Chul LIM, Jae-Eun PI, Min Ki RYU
  • Publication number: 20140158997
    Abstract: Provided is a dual-mode display including a substrate, and a plurality of sub pixels on the substrate. Each of the sub pixels may include an emissive device, a reflective optical filter provided on a surface of the emissive device, and an optical shutter provided on other surface of the emissive device.
    Type: Application
    Filed: June 18, 2013
    Publication date: June 12, 2014
    Inventors: Joon Tae Ahn, Jeong Ik Lee, Jaehyun Moon, Seung Koo Park, Nam Sung Cho, Doo-Hee Cho, Jun-Han Han, Joo Hyun Hwang, Jin Wook Shin, Jong Tae Lim, Chul Woong Joo, Jin Woo Huh, Chi-Sun Hwang, Hojun Ryu, Jae Bon Koo, Hye Yong Chu