Abstract: Systems and methods for providing a media device capabilities determination mechanism in a networked computing environment are provided. Some of today's operating systems and applications deliver a set of remoting features to enable a networked ecosystem of remote media consumption devices. These devices connect to the host and display a remoted media experience via remoting protocols and technologies. In this regard, the device capabilities determination mechanism of the invention enables a remote device to specify a custom set of media capabilities that should be remoted from the host to the remote device.

Abstract: An RC extraction tool estimates capacitances of conductors residing along parallel grid lines on each of a set vertically stacked layers of insulating material of an IC based on data contained in a IC layout file describing positions of structures forming the IC. The tool initially processes the layout file to generate a separate database for each layer. Each database includes a separate table for each grid line on its corresponding layer, and each table includes a separate entry for each conductor residing along that grid line containing data indicating dimensions and a position of its corresponding conductor along that grid line. The tool processes the databases for each layer in ascending order to estimate capacitances between conductors on that layer and to generate set of data structures mapping the amount of conductor surface area on that layer to areas of layers above that layer, and to areas of layers below that layer in which conductors reside.

Abstract: A clock tree synthesis (CTS) tool determines how to position a hierarchy of buffers for fanning out a clock signal to clocked devices (“sinks”) within an integrated circuit (IC). The tool first clusterizes the sinks and places a lowest level fan-out buffer near each cluster. The tool then iteratively places progressively higher level buffers by clusterizing a last-placed buffer level and then placing a next higher level buffer near the centroid of each lower level buffer cluster, until the tool has placed buffers at a mid-level for which variation in path distances between that level and a next higher buffer level exceeds a predetermined limit. The CTS tool then places a top level buffer at the centroid of the mid-level buffers, divides the layout into partitions, each containing a similar number of mid-level buffers, and then places a second-highest level buffer in each partition.

Abstract: A system and method providing electronic registration and maintenance of business directory listings and advertisements. In a computer system hosting an online business directory, it is advantageous to provide interested businesses with the ability to register their business listing information and/or advertisements such that the user may have direct input into the categorization the business listing(s) or advertisement(s) in the business directory. In an illustrative implementation, the system and methods of the present invention may be realized as an Internet based registration computing application cooperating with a business directory storing and displaying business directory listing information. This registration computing application may be employed as part of an Internet business directory listing information offering deployed on a Web site that offers business listing information services.

Abstract: A bandpass filter containing specific combinations of the dyes to yield filters which are adapted to selectively transmit predetermined primary color wavelengths of an electromagnetic spectrum as well as selectively absorb wavelengths other than the predetermined primary color wavelengths. The multiple bandpass filters are employed to improve the images on CRT screens and plasma display panels.

Abstract: A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.

Abstract: A bandpass filter containing specific combinations of the dyes to yield filters which are adapted to selectively transmit predetermined primary color wavelengths of an electromagnetic spectrum as well as selectively absorb wavelengths other than the predetermined primary color wavelengths. The multiple bandpass filters are employed to improve the images on CRT screens and plasma display panels.

Abstract: A clock tree synthesizer alters a clock tree design to balance a clock tree receiving and distributing one or more clock signals to many clocked devices (“sinks”) within an integrated circuit, wherein the clock tree includes one or more crossover and reconvergence points at outputs of multiplexers receiving clock signals via different paths through the clock tree. The clock tree synthesizer balances the clock tree by first balancing the subtree downstream of each multiplexer and then representing the multiplexer and the subtree with a separate macro for each multiplexer input, each macro representing the path delay from the corresponding multiplexer input to the sinks receiving clock signal inputs via the subtree. When the clock tree includes crossover points, the macros split the clock tree into a separate tree for each clock signal.

Abstract: A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate. The base level partitions include syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition. In accordance with the method, a plurality of independently balanced subtrees are separately synthesized. Each subtree resides within the area occupied by a separate base level partition and includes a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area. Thereafter a top level portion of the clock tree is synthesized.

Abstract: Described herein is a technology for in the realm of digital video broadcast technology or other such technology. One implementation, described herein, relates to broadcasting web content to client devices in a DVB (digital video broadcast) environment using rotational sequences of data modules (e.g., DSMCC carousels). One implementation, described herein, relates to emulating an interactive browsing experience of web content over a broadcast channel. One implementation, described herein, relates to the client device “smartly” caching select portions of the web content being broadcast. The scope of the present invention is pointed out in the appending claims.

Abstract: A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate, The base level partitions include syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition. In accordance with the method, a plurality of independently balanced subtrees are separately synthesized. Each subtree resides within the area occupied by a separate base level partition and includes a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area. Thereafter a top level portion of the clock tree is synthesized.

Abstract: A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.

Abstract: Signal paths within an integrated circuit (IC) are formed by cells and nets interconnecting the cells. A separate path delay is estimated for each of many signal paths within an IC by setting the path delay value to a sum of estimated delays through each net and cell forming the signal path. To compute path delays through the nets, RC extraction data contained in a database indicating estimated impedances of portions of all of nets of the IC is sequentially read out of the database on a net-by-net basis. As the RC extraction data for each net is read out, a path delay is computed based on that data for each section of the net that is included in any of the signal paths for which path delay is to be estimated. Data representing the path delay for each signal path is then incremented by an amount equal to the computed path delay of each section of that net, if any, forming a part of that signal path.

Abstract: A gated clock tree including a hierarchy of gates is synthesized by separately synthesizing a subtree residing under each gate, starting with the subtrees residing under gates at lowest level of the hierarchy and working upwards though the gate hierarchy. To design a subtree under a selected gate at any given level of the gate hierarchy, a centroid of a set of all downstream sinks and gates residing at a next lower level of the hierarchy that are to receive the clock signal via the selected gate is initially determined. A set of subtree endpoints are then established, each residing between the centroid and a corresponding sink or gate of the set of downstream sinks and gates. A balanced subtree is then designed to convey the clock signal from the selected gate to each subtree endpoint, and a separate signal path is designed to convey the clock signal from each subtree endpoint to a corresponding downstream sink or gate of the set.

Abstract: A system and method for electronically controlling the temperature of a pump laser or laser diode controls temperature uses methods of sourcing drive current. Further, the system shuts off the laser diode and/or a thermoelectric cooler when the temperature of the pump laser exceeds a predetermined amount.

Abstract: A bandpass filter containing specific red dyes alone or in combination with other dyes selectively transmits predetermined primary color wavelengths as well as selectively absorbs wavelengths other than the predetermined primary color wavelength. The filter is particularly useful for enhancing the contrast of color plasma displays by absorbing visible light emitted at 590 nm from the display.

Abstract: An optical waveguide comprising a first polymeric layer and a second polymeric layer adjacent to the first polymeric layer and a method for making the optical waveguide are disclosed. The first polymeric layer has a refractive index of n1 and solubility S1 in a first solvent. The second polymeric layer has a refractive index of n2 and solubility S2 in the first solvent. In the optical waveguide, n1 ≠n2 and S1/S2 is at least 5.

Abstract: A bandpass filter containing specific combinations of the dyes to yield filters which are adapted to selectively transmit predetermined primary color wavelengths of an electromagnetic spectrum as well as selectively absorb wavelengths other than the predetermined primary color wavelengths. The multiple bandpass filters are employed to improve the images on CRT screens and plasma display panels.

Abstract: An inline fiber optic polarization combiner/divider is proposed for use in fiber optic communications. It utilizes a polarizing beam splitting cube (PBSC) or a birefringent displacer located between a pair of collimating lenses. A reflecting film (either external or directly applied to one of the faces of the PBSC or birefringent displacer) is used to completely reflect one of the two polarizations and is positioned such that the optical path length between the lens and the reflecting film is equal to one focal length in order to accomplish an optical path where the input and output optical fibers are in-line with the package.

Abstract: An optical waveguide comprising a first polymeric layer and a second polymeric layer adjacent to the first polymeric layer and a method for making the optical waveguide are disclosed. The first polymeric layer has a refractive index of n1 and solubility S1 in a first solvent. The second polymeric layer has a refractive index of n2 and solubility S2 in the first solvent. In the optical waveguide, n1≠n2 and S1/S2 is at least 5.