Abstract: A heat dissipation device includes a housing, a heat dissipation plate, a first fan and at least two second fans. The housing has a first sidewall and a second sidewall that are opposite to each other. The first sidewall has a first opening area and the second sidewall has a second opening area which is facing the first opening area. The heat dissipation plate is located inside the housing and covers at least one heat source. An opening that corresponds to the first opening area and contains the first fan penetrates through the heat dissipation plate. Each of the at least two second fans that include airflow exits facing away from the first fan is located nearby the heat dissipation plate. The housing includes side surfaces that connect the first sidewall and the second sidewall and have three side opening areas that are facing different directions.

Abstract: A method includes transferring an inner pod of a carrier out from an outer pod of the carrier into a lithography exposure apparatus, the inner pod containing a reticle including a reflective multilayer and a pellicle underlying the reflective multilayer; detecting a condition of the pellicle using a metrology device positioned on a base plate of the inner pod during transferring the inner pod in the lithography exposure apparatus; determining whether the condition of the pellicle is acceptable; issuing a warning when the condition of the pellicle is not acceptable.

Abstract: A circuit includes a first power node having a first voltage level, a second power node having a second voltage level different from the first voltage level, a reference node having a reference voltage level, a master latch that outputs a first bit based on a received bit, a slave latch that outputs a second bit based on the first bit and an output bit based on a selected one of the first bit or a third bit, a first level shifter that outputs the third bit based on a complementary bit pair, and a retention latch including a second level shifter and a pair of inverters that outputs the complementary bit pair based on the second bit. The slave latch and the first level shifter are coupled between the first power and reference nodes, and the retention latch is coupled between the second power and reference nodes.

Abstract: A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

Abstract: A mobile device with high radiation efficiency includes a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, and a dielectric substrate. The first radiation element has a feeding point. The second radiation element is coupled to the first radiation element. The first radiation element is coupled through the third radiation element to the ground element. The fourth radiation element is coupled between the first radiation element and the third radiation element. The first radiation element, the second radiation element, the third radiation element, and the fourth radiation element are disposed on the dielectric substrate. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, and the fourth radiation element.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of an apparatus; and securing the wafer to the electrostatic chuck by: securing a first wafer region of the wafer to a first chuck region of the electrostatic chuck by applying a first voltage at a first time. The method further includes securing a second wafer region of the wafer to a second chuck region of the electrostatic chuck by applying a second voltage at a second time different from the first time; and processing the wafer by the apparatus while the wafer is secured to the electrostatic chuck.

Abstract: A mobile device supporting wideband operations includes a first radiation element, a second radiation element, a third radiation element, and a dielectric substrate. The first radiation element has a feeding point. The second radiation element is coupled to the ground voltage. The first radiation element is at least partially surrounded by the second radiation element. The feeding point is coupled through the third radiation element to the ground voltage. The first radiation element, the second radiation element, and the third radiation element are disposed on the dielectric substrate. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of an apparatus; and securing the wafer to the electrostatic chuck by: securing a first wafer region of the wafer to a first chuck region of the electrostatic chuck by applying a first voltage at a first time. The method further includes securing a second wafer region of the wafer to a second chuck region of the electrostatic chuck by applying a second voltage at a second time different from the first time; and processing the wafer by the apparatus while the wafer is secured to the electrostatic chuck.

Abstract: Systems and methods are described for reporting capacitance of a capacitor of a power backup circuit comprising a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs). The system may also include a bleeder resistor and a voltage detection circuit. When capacitance monitoring is active, a first MOSFET may be turned off, causing the capacitor to be discharged via the bleeder resistor. After predetermined time intervals, a first drain voltage and a second drain voltage of the first MOSFET may be determined using the voltage detection circuit. The drain voltage readings at the different times may be used to determine the capacitance of the capacitor, which may be used to generate and transmit a report on capacitor performance and status.

Abstract: Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.

Abstract: An electronic wake-up device and a wake-up method thereof are provided. The electronic wake-up device includes: a power switch device, an electronic device, a gravity sensor, and a wake-up circuit. The wake-up circuit is coupled to the gravity sensor and the electronic device. The wake-up circuit is configured to generate an execution signal according to a sensing activation signal, and generate an electronic device control signal according to the execution signal and a gravity signal to wake up the electronic device.

Abstract: An embodiment of the invention provides a method for a location tracking, applied to a mobile device, an indoor access point (AP) and at least one indoor Internet of Things (IoT) device, comprising: receiving, by the indoor AP, a first set of location information of the mobile device from the mobile device at outdoor, wherein the first set of location information is determined according to a Global Navigation Satellite System (GNSS); determining, by the indoor AP, a second set of location information of the indoor AP according to the first set of location information; determining, by the indoor AP, a third set of location information of the at least one indoor IoT device according to the second set of location information; and transmitting, by the indoor AP, the third set of location information to the at least one indoor IoT device.

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Abstract: This document describes systems and techniques for simulating the touch of a human finger in manipulating an interface device, such as a touchscreen included in a mobile phone or other computing device. The systems and techniques include an artificial finger configured to be received and manipulated by a robotic actuator to simulate surface engagement, mechanical force, and electrical conductivity of a human finger engaging the touchscreen at varied touch angles and/or mechanical pressures. The systems and techniques thereby provide for rigorous and repeatable testing of an electrical and mechanical response of the touchscreen to simulated user inputs without involving a human test operator.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: The present invention provides a short-circuit probe card, including: a substrate having an upper surface and a lower surface; a plurality of first contacts formed on the upper surface; and a plurality of second contacts formed on the lower surface and connected to the plurality of first contacts. The first contacts and second contacts are all grounded.

Abstract: A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.