Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.

Abstract: A driving voltage generating device includes a temperature detector, a controlling circuitry, a voltage generator, and an output stage circuitry. The temperature detector is coupled to a control terminal of a power transistor and is configured to generate temperature detection information by detecting an ambient temperature. The controlling circuitry is coupled to the temperature detector and generates an activation signal by determining whether the ambient temperature is abnormal according to the temperature detection information. The voltage generator generates an operation power according to the activation signal. The output stage circuitry is coupled to the voltage generator, generates a driving voltage according to the operation power, and provides the driving voltage to the control terminal of the power transistor.

Abstract: A temperature sensing device includes a resistor string and a control circuitry. The resistor string includes a variable resistor, a first resistor, and a second resistor which are coupled in series with each other. The resistor string is coupled between a sensing end and a reference ground voltage. The first resistor and the second resistor are coupled to a monitoring end to provide a monitoring voltage. The control circuitry compares the monitoring voltage with a plurality of reference voltages to generate sensing temperature information, and generate adjustment information according to the sensing temperature information. The control circuitry adjusts a resistance provided by the variable resistor according to the adjustment information. The first resistor is a polysilicon resistor, and the second resistor is a silicon carbide diffusion resistor.

Abstract: An electronic device and a temperature detection device thereof are provided. The temperature detection device includes a first resistor, a second resistor, and an operation circuit. The first resistor and the second resistor are coupled in series between a detection end and a first voltage. The first resistor and the second resistor divide a detection voltage on the detection end to generate a monitoring voltage. The operation circuit compares the monitoring voltage with a plurality of reference voltages to generate a plurality of comparison results. The operation circuit performs an operation on the comparison results to generate detection temperature information. The first resistor is a poly-silicon resistor and the second resistor is a silicon carbon (SiC) diffusion resistor.

Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.

Abstract: A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 ?m to 600 ?m, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.

Abstract: Methods, systems, and apparatuses for image segmentation are provided. For example, a computing device may obtain an image, and may apply a process to the image to generate input image feature data and input image segmentation data. Further, the computing device may obtain reference image feature data and reference image classification data for a plurality of reference images. The computing device may generate reference image segmentation data based on the reference image feature data, the reference image classification data, and the input image feature data. The computing device may further blend the input image segmentation data and the reference image segmentation data to generate blended image segmentation data. The computing device may store the blended image segmentation data within a data repository. In some examples, the computing device provides the blended image segmentation data for display.

Abstract: The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.

Abstract: A silicon carbide semiconductor power transistor includes a silicon carbide substrate, a first drift layer, a second drift layer on the substrate with V-grooves, buried doped regions in the first drift layer below the V-grooves, gates in the V-grooves, a gate insulation layer, a delta doping layer, a well region, source regions, well pick-up regions, conductive trenches, and doping portions. Each of the buried doped regions is a predetermined distance from a bottom of each of the V-grooves. The delta doping layer is disposed in the second drift layer, and the V-grooves are across the delta doping layer. The conductive trenches are disposed in the second drift layer, and each of the conductive trenches passes through the well pick-up regions and contacts with the well region. The doping portions are respectively on sidewalls of the conductive trenches in the well region.

Abstract: An imaging lens assembly of an optical verification system with a FOV greater than 120 degrees, and includes optical lenses from an object side to an image side. The one of the optical lens being the closest to the object side includes: an object side surface and an image side surface of an optical zone; an object side surface of a non-optical-zone surrounding the object side surface of the optical zone; an image side surface of a non-optical zone surrounding the image side surface of the optical zone; and a first connection portion disposed between the image side surface of the optical-zone and the image side surface of the non-optical zone, wherein a first angle between a tangential direction of a surface of the first connection portion and the radial direction is in a range of 15 to 50 degrees.

Abstract: A wearable authentication system is provided. The wearable authentication system includes a head-mounted device and a ring device. The head-mounted device includes a first network module and a camera. The first network module sends an authentication request. The camera is configured to provide an image of a hand of a user. The ring device includes an inertial measurement unit, a second network module and a biometric sensor. The inertial measurement unit provides an inertial measurement value of the ring device. The second network module receives the authentication request. The biometric sensor gathers biometric information from the user based on the authentication request. The wearable authentication system tracks a position of the ring device based on at least one of the image and the inertial measurement value. The second network module sends authentication information based on the biometric information and the inertial measurement value to the first network module.

Abstract: A method of manufacturing a silicon carbide semiconductor power device is provided. In the method, the power device in high voltage (HV) region and CMOS device in the low voltage (LV) region are formed together, so the cost and time can be saved efficiently. First, a first drift layer is formed on a substrate, and then a shielding region is formed in the first drift layer. The shielding region includes a continuous region in the LV region. Then, a second drift layer is formed on the first drift layer. A pick-up region is formed in the second drift layer, wherein the pick-up region connects to the continuous region of the shielding region, and then NMOS and PMOS in the LV region and the power device in HV region are formed simultaneously. NMOS and PMOS are surrounded by the pick-up region and the continuous region, thereby minimizing body effect.

Abstract: A silica aerogel-containing polyester masterbatch includes a polyethylene terephthalate resin, a silica aerogel powder, and a dispersing agent. The silica aerogel powder is dispersed in the polyethylene terephthalate resin, and is present in an amount ranging from 5 wt % to 30 wt % based on 100 wt % of the silica aerogel-containing polyester masterbatch. The dispersing agent is dispersed in the polyethylene terephthalate resin, is selected from the group consisting of a paraffin oil, a silane compound, a wax including C28-C32 straight chain monoacids, and combinations thereof, and is present in an amount ranging from 0.1 wt % to 4.0 wt % based on 100 wt % of the silica aerogel-containing polyester masterbatch. A method for preparing the silica aerogel-containing polyester masterbatch, and a silica aerogel-containing polyester fiber made from the same are also disclosed.

Abstract: A short-circuit protection circuitry is adapted for a power transistor. The short-circuit protection circuitry includes a first diode, a first resistor, a voltage dividing circuit, a gate voltage generator, a pull-down circuit, and a control signal generator. The first diode is coupled to a drain of the power transistor. The first resistor is coupled between the first diode and the power transistor. The voltage dividing circuit is coupled between a gate and a source of the power transistor to generate a dividing voltage. The gate voltage generator provides a gate voltage to the gate of the power transistor according to a first driving signal and a second driving signal. The pull-down circuit pulls down the gate voltage according to a control signal. The control signal generator generates the control signal according to the first driving signal, a voltage on the anode of the first diode and the dividing voltage.

Abstract: A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.