Abstract: A memory device includes a two-dimensional array of access transistors located on a semiconductor substrate; metal interconnect structures embedded in dielectric material layers and electrical connected to electrical nodes of the access transistors; and a two-dimensional array of resistive memory structures embedded in the dielectric material layers. The metal interconnect structures include two first source lines located at a first metal line level and laterally extending along a first horizontal direction; a second source line located at a second metal line level and laterally extending along the first horizontal direction; and a vertical connection structure including a plurality of interconnection via structures and at least one line-level metal structure and providing a vertical electrical connection between the two first source lines and the second source line.

Abstract: A method for manufacturing a semiconductor device includes: forming an etch stop layer with an opening; forming a barrier layer on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion to be inserted into the opening of the etch stop layer; forming a bottom electrode layer on the layer portion of the barrier layer opposite to the etch stop layer; forming a ferroelectric layer on the bottom electrode layer opposite to the barrier layer; and forming a top electrode layer on the ferroelectric layer opposite to the bottom electrode layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.

Abstract: A semiconductor structure includes a ferroelectric layer and a semiconductor layer. Thee ferroelectric layer has a first surface and a second surface opposite to the first surface. The semiconductor layer is formed on one of the first surface and the second surface.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: The present disclosure relates to a ferroelectric memory device that includes a bottom electrode, a ferroelectric structure overlying the bottom electrode, and a top electrode overlying the ferroelectric structure where the bottom electrode includes molybdenum.

Abstract: A ferroelectric tunnel junction is formed, comprising a plurality of layers including at least a bottom electrode layer, a top electrode layer, and at least one ferroelectric layer disposed between the bottom electrode layer and the top electrode layer. The at least one ferroelectric layer comprises a ferroelectric material. At least one layer of the plurality of layers is in contact with the ferroelectric layer and has a coefficient of thermal expansion that is at least 25% lower than a coefficient of thermal expansion of the ferroelectric layer; and inducing ferroelectric phase crystallization in the ferroelectric layer by annealing the plurality of layers.

Abstract: Some embodiments relate to a method of forming an integrated chip, including forming a first wire level over a substrate; depositing an etch stop layer over the first wire level; etching the etch stop layer to form an opening over the first wire level; depositing a barrier layer over the etch stop layer, the barrier layer extending into the opening; depositing a first conductive layer over the barrier layer and in the opening; performing a planarization into the first conductive layer to flatten a top of the first conductive layer, wherein the planarization stops before reaching the barrier layer; depositing a data storage layer and a second conductive layer over the first conductive layer; and patterning the barrier layer, the first conductive layer, the data storage layer, and the second conductive layer to form a memory cell at the opening.

Abstract: A ferroelectric tunnel junction (FTJ) includes bottom and top electrodes and a ferroelectric layer disposed between the bottom and top electrodes. A dielectric material is disposed in a space between a peripheral area of the ferroelectric layer and a sidewall of the top electrode. At least one conformal dielectric spacer is deposited. The FTJ is annealed to induce ferroelectric phase crystallization in the ferroelectric layer. The depositing at least one conformal dielectric spacer includes at least one of: (i) prior to the disposing of the dielectric material, depositing an inner conformal dielectric spacer on the peripheral area of the ferroelectric layer and on the sidewall of the top electrode, and/or (ii) after the disposing of the dielectric material, depositing an outer conformal dielectric spacer on dielectric material and on a sidewall of the peripheral area of the ferroelectric layer.

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Abstract: A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells.

Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.