Abstract: Various embodiments of the present disclosure are directed towards a memory cell in which an interfacial layer is on a bottom of a ferroelectric layer, between a bottom electrode and a ferroelectric layer. The interfacial layer is a different material than the bottom electrode and the ferroelectric layer and has a top surface with high texture uniformity compared to a top surface of the bottom electrode. The interfacial layer may, for example, be a dielectric, metal oxide, or metal that is: (1) amorphous; (2) monocrystalline; (3) crystalline with low grain size variation; (4) crystalline with a high percentage of grains sharing a common orientation; (5) crystalline with a high percentage of grains having a small grain size; or 6) any combination of the foregoing. It has been appreciated that such materials lead to high texture uniformity at the top surface of the interfacial layer.

Abstract: A structure includes a semiconductor substrate, a gate structure, a source/drain feature, a source/drain contact, a dielectric layer, and a ferroelectric random access memory (FERAM) structure. The gate structure is on the semiconductor substrate. The source/drain feature is adjacent to the gate structure. The source/drain contact lands on the source/drain feature. The dielectric layer spans the source/drain contact. The FeRAM structure is partially embedded in the dielectric layer and includes a bottom electrode layer on the source/drain contact and having an U-shaped cross section, a ferroelectric layer conformally formed on the bottom electrode layer, and a top electrode layer over the ferroelectric layer.

Abstract: A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, a memory gate, and a data storage element. The semiconductor substrate includes a memory well which has two source/drain regions and a channel region between the source/drain regions. The memory gate is disposed above the channel region. The data storage element includes a ferroelectric material, and is disposed around the memory gate to separate the memory gate from the channel region.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a bottom electrode layer over a substrate; depositing a ferroelectric layer over the bottom electrode layer; depositing a first top electrode layer over the ferroelectric layer, wherein the first top electrode layer comprises a first metal; depositing a second top electrode layer over the first top electrode layer, wherein the second top electrode layer comprises a second metal, and a standard reduction potential of the first metal is greater than a standard reduction potential of the second metal; and removing portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer to form a memory stack, the memory stack comprising remaining portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer.

Abstract: A structure includes a semiconductor substrate, a gate structure, a source/drain feature, a source/drain contact, a dielectric layer, and a ferroelectric random access memory (FERAM) structure. The gate structure is on the semiconductor substrate. The source/drain feature is adjacent to the gate structure. The source/drain contact lands on the source/drain feature. The dielectric layer spans the source/drain contact. The FeRAM structure is partially embedded in the dielectric layer and includes a bottom electrode layer on the source/drain contact and having an U-shaped cross section, a ferroelectric layer conformally formed on the bottom electrode layer, and a top electrode layer over the ferroelectric layer.

Abstract: The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.

Abstract: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.

Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower insulating structure disposed over a lower dielectric structure surrounding an interconnect. The lower insulating structure has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure, a data storage structure is disposed on first interior sidewalls and an upper surface of the bottom electrode, and a top electrode is disposed on second interior sidewalls and an upper surface of the data storage structure. An interconnect via is on an upper surface of the top electrode. A bottom surface of the bottom electrode is laterally outside of a bottom surface of the interconnect via.

Abstract: A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.