Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: A user equipment (UE) is configured to implement selective call initiation delay responsive to detection of a contemporaneous handover process. When a user provides input indicating initiation of a packet-switched call, the UE determines whether there is a handover process ongoing. If not, a call initiation message (e.g., a SIP INVITE message) is transmitted without further delay. However, if a handover process is ongoing at the time of the user input, the UE refrains from promptly transmitting the call initiation message and starts a timer of a predetermined duration to provide additional time for the handover process to complete. Responsive to the timer expiring or to the handover process completing before the timer expires, the UE then promptly transmits the call initiation message to initiate establishment of the packet-switched call over whatever network to which the UE is currently attached.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A hard mask (HM) layer is formed over a dielectric layer over a substrate. A plurality of mandrels are formed over the HM layer. A spacer layer including a plurality of trenches between the mandrels is formed over the HM layer and the mandrels. A first and a second portion of the trenches is filled by a first and a second block material, respectively. A third portion of the trenches is free from filled by these block materials. At least a first opening is formed in the spacer layer. At least a second opening is formed by removing a portion of the mandrels. The HM layer is etched through the first and the second openings. The dielectric layer is patterned. A plurality of conductive lines are formed in the patterned dielectric layer.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.

Abstract: A method and structure for forming semiconductor device includes forming a first opening in a dielectric layer to expose a source/drain region. In some embodiments, the method further includes depositing a first metal layer in the opening and over the source/drain region. Thereafter, in some examples, the method further includes performing an annealing process to modulate a grain size of the first metal layer. In various embodiments, the method further includes depositing a second metal layer over the annealed first metal layer. In some embodiments, the second metal layer has a substantially uniform phase.

Abstract: An information handling system may include a processor, one or more audio speakers configured to play back audible audio signals, and a basic input/output system (BIOS) comprising a program of instructions comprising boot firmware configured to be the first code executed by the processor when the information handling system is booted or powered on in order to initialize the information handling system for operation. The BIOS may be further configured to monitor for an error occurring during execution of the BIOS and responsive to an error occurring during execution of the BIOS, cause the one or more audio speakers to play back a sequence of one or more multi-frequency audio signals encoding an identity of the error.

Abstract: A method includes forming an epitaxial stack including a first sacrificial layer, a channel layer, and a second sacrificial layer over a semiconductor substrate; patterning the epitaxial stack into a fin structure such that opposite first ends of the channel layer are exposed; recessing the opposite first ends of the channel layer; forming first dummy spacers on the recessed opposite first ends of the channel layer; forming an isolation structure in the fin structure; recessing a top surface of the isolation structure to a position lower than a bottom surface of the channel layer, such that opposite second ends of the channel layer are exposed; recessing the opposite second ends of the channel layer; forming second dummy spacers on the recessed opposite second ends of the channel layer; and replacing the first dummy spacers and the second dummy spacers with a metal gate structure.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.

Abstract: A method of modifying a layout for an integrated circuit (IC) includes: selecting, in the layout, a circuit region to be scaled; setting a fixed area including a fixed feature in the selected circuit region; and scaling the selected circuit region, without scaling the fixed area including the fixed feature, to obtain a modified layout for the IC.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a metallization layer. The metallization layer is disposed over the substrate. The metallization layer includes a first signal line, a second signal line, and a third signal line, wherein the first signal line, the second signal line, and the third signal line are arranged in a first row between a power rail and a ground rail parallel to the power rail. A first distance between the first signal line and the second signal line is different from a second distance between the second signal line and the third signal line. A method for manufacturing a semiconductor structure is also provided.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: A method includes assigning a default voltage value to a net in an integrated circuit (IC) schematic, generating a simulation voltage value of the net by performing a circuit simulation on the net using the assigned default voltage value, and modifying the IC schematic to include a voltage value associated with the net. The voltage value associated with the net and included in the modified IC schematic is based on a comparison between the assigned default voltage value and the simulation voltage value of the net.

Abstract: A vertical cavity surface emitting laser (VCSEL) including a first ohmic contact to the substrate formed on an upper surface of the device, instead of the conventional substrate bottom-side contact. The VCSEL is formed to include a hole made through the first distributed Bragg reflector (DBR) and into the material of the substrate itself. A metal layer is deposited at the bottom of the hole to contact the substrate, where the deposited metal layer creates a high quality ohmic contact by not also contacting the inner sidewalls of the hole (i.e., no “stringers” are formed within the hole).

Abstract: A method of making a semiconductor device includes determining a first scaling factor for a first region of a first device layout, wherein the first region comprises a first plurality of conductive patterns. The method further includes determining a second scaling factor for a second region of the first device layout, wherein the second region comprises a second plurality of conductive patterns, and the first device layout comprises an interconnect pattern extending from the first region to the second region. The method further includes generating a second device layout. Generating the second device layout includes adjusting the interconnect pattern based on the first scaling factor and the second scaling factor.

Abstract: A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.

Abstract: A method for forming a metal contact in a deep hole in a workpiece. A first hole is formed that extends from the upper surface of the workpiece to a substrate at the bottom of the hole. The hole is then filled with photoresist. Next, a photolithographic process is performed to create a second hole within the photoresist and to expose the substrate; and a wet etch is performed to remove a portion of the substrate. A layer of contact metal is then deposited on the surface of the photoresist. In the second hole, the metal layer is formed on the exposed surface of the substrate and on discontinuous portions of the photoresist on the sidewalls. A liftoff process is then used to remove the photoresist and the metal deposited on the photoresist while leaving the metal at the bottom of the second hole in contact with the substrate.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.