Patents by Inventor Chi-Wen Chang

Chi-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818611
    Abstract: Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an adhesion layer on the backside of the wafer, and forming a stress compensation layer on the adhesion layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 27, 2020
    Assignee: II-VI Delaware, Inc.
    Inventors: Kevin Chi-Wen Chang, David Hensley, William Wilkinson
  • Publication number: 20200285796
    Abstract: A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Chi-Wen CHANG, Jui-Feng KUAN
  • Patent number: 10763253
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Publication number: 20200272781
    Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 27, 2020
    Inventors: Feng-Ming Chang, Ruey-Wen Chang, Ping-Wei Wang, Sheng-Hsiung Wang, Chi-Yu Lu
  • Patent number: 10741250
    Abstract: A non-volatile memory device driving method, applicable to a non-volatile memory device comprising a row decoder and a memory array, comprises: utilizing the row decoder to transmit multiple word line signals to multiple word lines of the memory array; according to an address, utilizing the row decoder to switch a selected word line signal of the multiple word line signals from a predetermined voltage level to a program voltage level; utilizing the row decoder to switch at least one support word line signal of the multiple word line signals from the predetermined voltage level to a first pass voltage level; when the selected word line signal is remained at the program voltage level, utilizing the row decoder to switch the at least one support word line signal from the first pass voltage level to a higher second pass voltage level.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 11, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsing-Wen Chang, Yao-Wen Chang, Chi-Yuan Chin
  • Patent number: 10685161
    Abstract: A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Wen Chang, Jui-Feng Kuan
  • Patent number: 10658234
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Hsiu Hung, Sung-Li Wang, Pei-Wen Wu, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi-On Chui
  • Publication number: 20200151382
    Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
  • Publication number: 20200145658
    Abstract: A post processing apparatus includes a super-resolution (SR) filtering circuit and a loop restoration (LR) filtering circuit. The SR filtering circuit applies SR filtering to a processing result of a preceding circuit. The LR filtering circuit applies LR filtering to a processing result of the SR filtering circuit. Before the SR filtering circuit finishes SR filtering of all pixels of a frame that are generated by the preceding circuit, the LR filtering circuit starts LR filtering of pixels that are derived from applying SR filtering to pixels included in the frame.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 7, 2020
    Inventors: Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Chi-Hung Chen, Kai-Chun Lin, Chih-Wen Yang, Hsuan-Wen Peng
  • Publication number: 20200125696
    Abstract: A method includes assigning a default voltage value of a voltage domain in an integrated circuit (IC) schematic to a net in the voltage domain, generating a simulation voltage value of the net by performing a circuit simulation on the net, and modifying the IC schematic to include a voltage value associated with the net, based on the simulation voltage value of the net.
    Type: Application
    Filed: September 10, 2019
    Publication date: April 23, 2020
    Inventors: Chi-Wen CHANG, Jui-Feng KUAN
  • Patent number: 10621722
    Abstract: The present invention disclosed an iterative analyzing method, which can detect the lesion in the image quickly. In brief, the iterative analysis method of the medical image disclosed by the present invention is roughly as follows: first, the original spectral image cube is expanded into a spectral image cube by a method of nonlinear dimensional-expansion, and then detecting the target's subpixel by the method of constrained energy minimization to produce an abundance image; the abundance image is fed back to the spectral image cube for create another spectral image cube by the nonlinear method. Furthermore, the abundance image is only used for detecting the subpixel of the target and does not include any spatial information, so, in order to obtain the spatial information of spectral image, it obtains the spatial information around the subpixel by using a blurring tool such as a Gaussian filter.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: April 14, 2020
    Assignee: TAICHUNG VETERANS GENERAL HOSPITAL
    Inventors: Chein-I Chang, Chi-Chang Clayton Chen, Jyh Wen Chai, Hsian-Min Chen
  • Publication number: 20200062738
    Abstract: A compound for inhibiting BMI-1/MCL-1 having a structure of Formula (I), wherein the various groups are as described. A pharmaceutical composition for treating cancer includes an effective amount of a compound of Formula (I).
    Type: Application
    Filed: April 30, 2018
    Publication date: February 27, 2020
    Applicants: Development Center for Biotechnology, National Yang-Ming University
    Inventors: Cheng-Wen Wu, Erh-Hsuan Jiann Lin, Chi-Ying Huang, Jia-Ming Chang, Shih-Hsien Chuang, Hui-Jan Hsu, Wei-Wei Chen
  • Publication number: 20200058762
    Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.
    Type: Application
    Filed: July 10, 2019
    Publication date: February 20, 2020
    Inventors: Chi-Wen HSIEH, Chien-Ping HUNG, Chi-Kang CHANG, Shih-Chi FU, Kuei-Shun CHEN
  • Publication number: 20200057834
    Abstract: A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.
    Type: Application
    Filed: November 29, 2018
    Publication date: February 20, 2020
    Inventors: Chi-Wen CHANG, Jui-Feng KUAN
  • Patent number: 10540475
    Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
  • Publication number: 20200020583
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiang CHAO, Min-Hsiu HUNG, Chun-Wen NIEH, Ya-Huei LI, Yu-Hsiang LIAO, Li-Wei CHU, Kan-Ju LIN, Kuan-Yu YEH, Chi-Hung CHUANG, Chih-Wei CHANG, Ching-Hwanq SU, Hung-Yi HUANG, Ming-Hsing TSAI
  • Patent number: 10536587
    Abstract: The present invention relates to a document scanning apparatus which is composed of an automatic document feeding device and an image capturing device. The document scanning apparatus establishes a private area network between the automatic document feeding device and the image capturing device, and causes the automatic document feeding device to send a message to the image capturing device. When the message is received, said image capturing device performs corresponding operations in response to the message. Said operations may comprise, for example adjusting the relative position between the image capturing device and the automatic document feeding device or doing multi-documents scan.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 14, 2020
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Chi Wen Chen, Chi Cheng Chuang, Hung Ming Chou, Lung Chen, Yao Shuo Chang
  • Publication number: 20200011882
    Abstract: A method for calculating glomerular filtration rate (GFR) is revealed. A circumference of a patent's neck is measured and then is substituted into an exponential formula together with clinical factors and patient's age for estimating GFR. The present method has a better performance compared with methods for evaluating renal function by GFR available now. The methods available now have poor performance in prediction of loss of renal function at early stage. Some patients are diagnosed at an advanced stage so that they miss the opportunity of early treatment.
    Type: Application
    Filed: August 14, 2018
    Publication date: January 9, 2020
    Inventors: PO-JEN HSIAO, YUN-WEN SHIH, CHI-MING CHU, SHIH-TAI CHANG
  • Publication number: 20200006498
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Publication number: 20200006325
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng